2023-08-30 17:31:07 +02:00
|
|
|
/* SPDX-License-Identifier: GPL-2.0 */
|
|
|
|
|
/*
|
|
|
|
|
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#ifndef QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
|
|
|
|
|
#define QCOM_PHY_QMP_PCS_PCIE_V5_20_H_
|
|
|
|
|
|
|
|
|
|
/* Only for QMP V5_20 PHY - PCIe PCS registers */
|
|
|
|
|
#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
|
|
|
|
|
#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084
|
|
|
|
|
#define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
|
|
|
|
|
#define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0
|
|
|
|
|
#define QPHY_V5_20_PCS_PCIE_PRESET_P10_POST 0x0e0
|
2023-10-24 12:59:35 +02:00
|
|
|
#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc
|
2023-08-30 17:31:07 +02:00
|
|
|
#define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
|
|
|
|
|
#define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c
|
|
|
|
|
#define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184
|
2023-10-24 12:59:35 +02:00
|
|
|
#define QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2 0xa24
|
|
|
|
|
#define QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2 0xa28
|
2023-08-30 17:31:07 +02:00
|
|
|
|
|
|
|
|
#endif
|
