354 lines
9.5 KiB
C
354 lines
9.5 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* QLogic iSCSI HBA Driver
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* Copyright (c) 2003-2013 QLogic Corporation
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*/
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#ifndef __QL483XX_H
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#define __QL483XX_H
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/* Indirectly Mapped Registers */
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#define QLA83XX_FLASH_SPI_STATUS 0x2808E010
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#define QLA83XX_FLASH_SPI_CONTROL 0x2808E014
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#define QLA83XX_FLASH_STATUS 0x42100004
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#define QLA83XX_FLASH_CONTROL 0x42110004
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#define QLA83XX_FLASH_ADDR 0x42110008
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#define QLA83XX_FLASH_WRDATA 0x4211000C
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#define QLA83XX_FLASH_RDDATA 0x42110018
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#define QLA83XX_FLASH_DIRECT_WINDOW 0x42110030
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#define QLA83XX_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA))
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/* Directly Mapped Registers in 83xx register table */
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/* Flash access regs */
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#define QLA83XX_FLASH_LOCK 0x3850
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#define QLA83XX_FLASH_UNLOCK 0x3854
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#define QLA83XX_FLASH_LOCK_ID 0x3500
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/* Driver Lock regs */
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#define QLA83XX_DRV_LOCK 0x3868
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#define QLA83XX_DRV_UNLOCK 0x386C
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#define QLA83XX_DRV_LOCK_ID 0x3504
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#define QLA83XX_DRV_LOCKRECOVERY 0x379C
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/* IDC version */
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#define QLA83XX_IDC_VER_MAJ_VALUE 0x1
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#define QLA83XX_IDC_VER_MIN_VALUE 0x0
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/* IDC Registers : Driver Coexistence Defines */
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#define QLA83XX_CRB_IDC_VER_MAJOR 0x3780
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#define QLA83XX_CRB_IDC_VER_MINOR 0x3798
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#define QLA83XX_IDC_DRV_CTRL 0x3790
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#define QLA83XX_IDC_DRV_AUDIT 0x3794
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#define QLA83XX_SRE_SHIM_CONTROL 0x0D200284
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#define QLA83XX_PORT0_RXB_PAUSE_THRS 0x0B2003A4
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#define QLA83XX_PORT1_RXB_PAUSE_THRS 0x0B2013A4
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#define QLA83XX_PORT0_RXB_TC_MAX_CELL 0x0B200388
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#define QLA83XX_PORT1_RXB_TC_MAX_CELL 0x0B201388
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#define QLA83XX_PORT0_RXB_TC_STATS 0x0B20039C
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#define QLA83XX_PORT1_RXB_TC_STATS 0x0B20139C
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#define QLA83XX_PORT2_IFB_PAUSE_THRS 0x0B200704
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#define QLA83XX_PORT3_IFB_PAUSE_THRS 0x0B201704
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/* set value to pause threshold value */
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#define QLA83XX_SET_PAUSE_VAL 0x0
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#define QLA83XX_SET_TC_MAX_CELL_VAL 0x03FF03FF
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#define QLA83XX_RESET_CONTROL 0x28084E50
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#define QLA83XX_RESET_REG 0x28084E60
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#define QLA83XX_RESET_PORT0 0x28084E70
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#define QLA83XX_RESET_PORT1 0x28084E80
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#define QLA83XX_RESET_PORT2 0x28084E90
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#define QLA83XX_RESET_PORT3 0x28084EA0
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#define QLA83XX_RESET_SRE_SHIM 0x28084EB0
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#define QLA83XX_RESET_EPG_SHIM 0x28084EC0
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#define QLA83XX_RESET_ETHER_PCS 0x28084ED0
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/* qla_83xx_reg_tbl registers */
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#define QLA83XX_PEG_HALT_STATUS1 0x34A8
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#define QLA83XX_PEG_HALT_STATUS2 0x34AC
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#define QLA83XX_PEG_ALIVE_COUNTER 0x34B0 /* FW_HEARTBEAT */
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#define QLA83XX_FW_CAPABILITIES 0x3528
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#define QLA83XX_CRB_DRV_ACTIVE 0x3788 /* IDC_DRV_PRESENCE */
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#define QLA83XX_CRB_DEV_STATE 0x3784 /* IDC_DEV_STATE */
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#define QLA83XX_CRB_DRV_STATE 0x378C /* IDC_DRV_ACK */
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#define QLA83XX_CRB_DRV_SCRATCH 0x3548
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#define QLA83XX_CRB_DEV_PART_INFO1 0x37E0
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#define QLA83XX_CRB_DEV_PART_INFO2 0x37E4
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#define QLA83XX_FW_VER_MAJOR 0x3550
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#define QLA83XX_FW_VER_MINOR 0x3554
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#define QLA83XX_FW_VER_SUB 0x3558
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#define QLA83XX_NPAR_STATE 0x359C
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#define QLA83XX_FW_IMAGE_VALID 0x35FC
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#define QLA83XX_CMDPEG_STATE 0x3650
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#define QLA83XX_ASIC_TEMP 0x37B4
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#define QLA83XX_FW_API 0x356C
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#define QLA83XX_DRV_OP_MODE 0x3570
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#define QLA83XX_CRB_WIN_BASE 0x3800
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#define QLA83XX_CRB_WIN_FUNC(f) (QLA83XX_CRB_WIN_BASE+((f)*4))
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#define QLA83XX_SEM_LOCK_BASE 0x3840
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#define QLA83XX_SEM_UNLOCK_BASE 0x3844
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#define QLA83XX_SEM_LOCK_FUNC(f) (QLA83XX_SEM_LOCK_BASE+((f)*8))
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#define QLA83XX_SEM_UNLOCK_FUNC(f) (QLA83XX_SEM_UNLOCK_BASE+((f)*8))
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#define QLA83XX_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0))
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#define QLA83XX_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4))
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#define QLA83XX_MAX_LINK_SPEED(f) (0x36F0+(((f) / 4) * 4))
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#define QLA83XX_LINK_SPEED_FACTOR 10
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/* FLASH API Defines */
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#define QLA83xx_FLASH_MAX_WAIT_USEC 100
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#define QLA83XX_FLASH_LOCK_TIMEOUT 10000
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#define QLA83XX_FLASH_SECTOR_SIZE 65536
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#define QLA83XX_DRV_LOCK_TIMEOUT 2000
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#define QLA83XX_FLASH_SECTOR_ERASE_CMD 0xdeadbeef
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#define QLA83XX_FLASH_WRITE_CMD 0xdacdacda
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#define QLA83XX_FLASH_BUFFER_WRITE_CMD 0xcadcadca
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#define QLA83XX_FLASH_READ_RETRY_COUNT 2000
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#define QLA83XX_FLASH_STATUS_READY 0x6
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#define QLA83XX_FLASH_BUFFER_WRITE_MIN 2
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#define QLA83XX_FLASH_BUFFER_WRITE_MAX 64
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#define QLA83XX_FLASH_STATUS_REG_POLL_DELAY 1
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#define QLA83XX_ERASE_MODE 1
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#define QLA83XX_WRITE_MODE 2
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#define QLA83XX_DWORD_WRITE_MODE 3
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#define QLA83XX_GLOBAL_RESET 0x38CC
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#define QLA83XX_WILDCARD 0x38F0
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#define QLA83XX_INFORMANT 0x38FC
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#define QLA83XX_HOST_MBX_CTRL 0x3038
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#define QLA83XX_FW_MBX_CTRL 0x303C
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#define QLA83XX_BOOTLOADER_ADDR 0x355C
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#define QLA83XX_BOOTLOADER_SIZE 0x3560
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#define QLA83XX_FW_IMAGE_ADDR 0x3564
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#define QLA83XX_MBX_INTR_ENABLE 0x1000
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#define QLA83XX_MBX_INTR_MASK 0x1200
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/* IDC Control Register bit defines */
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#define DONTRESET_BIT0 0x1
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#define GRACEFUL_RESET_BIT1 0x2
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#define QLA83XX_HALT_STATUS_INFORMATIONAL (0x1 << 29)
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#define QLA83XX_HALT_STATUS_FW_RESET (0x2 << 29)
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#define QLA83XX_HALT_STATUS_UNRECOVERABLE (0x4 << 29)
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/* Firmware image definitions */
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#define QLA83XX_BOOTLOADER_FLASH_ADDR 0x10000
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#define QLA83XX_BOOT_FROM_FLASH 0
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#define QLA83XX_IDC_PARAM_ADDR 0x3e8020
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/* Reset template definitions */
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#define QLA83XX_MAX_RESET_SEQ_ENTRIES 16
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#define QLA83XX_RESTART_TEMPLATE_SIZE 0x2000
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#define QLA83XX_RESET_TEMPLATE_ADDR 0x4F0000
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#define QLA83XX_RESET_SEQ_VERSION 0x0101
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/* Reset template entry opcodes */
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#define OPCODE_NOP 0x0000
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#define OPCODE_WRITE_LIST 0x0001
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#define OPCODE_READ_WRITE_LIST 0x0002
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#define OPCODE_POLL_LIST 0x0004
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#define OPCODE_POLL_WRITE_LIST 0x0008
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#define OPCODE_READ_MODIFY_WRITE 0x0010
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#define OPCODE_SEQ_PAUSE 0x0020
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#define OPCODE_SEQ_END 0x0040
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#define OPCODE_TMPL_END 0x0080
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#define OPCODE_POLL_READ_LIST 0x0100
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/* Template Header */
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#define RESET_TMPLT_HDR_SIGNATURE 0xCAFE
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struct qla4_83xx_reset_template_hdr {
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__le16 version;
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__le16 signature;
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__le16 size;
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__le16 entries;
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__le16 hdr_size;
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__le16 checksum;
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__le16 init_seq_offset;
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__le16 start_seq_offset;
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} __packed;
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/* Common Entry Header. */
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struct qla4_83xx_reset_entry_hdr {
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__le16 cmd;
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__le16 size;
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__le16 count;
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__le16 delay;
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} __packed;
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/* Generic poll entry type. */
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struct qla4_83xx_poll {
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__le32 test_mask;
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__le32 test_value;
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} __packed;
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/* Read modify write entry type. */
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struct qla4_83xx_rmw {
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__le32 test_mask;
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__le32 xor_value;
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__le32 or_value;
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uint8_t shl;
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uint8_t shr;
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uint8_t index_a;
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uint8_t rsvd;
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} __packed;
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/* Generic Entry Item with 2 DWords. */
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struct qla4_83xx_entry {
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__le32 arg1;
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__le32 arg2;
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} __packed;
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/* Generic Entry Item with 4 DWords.*/
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struct qla4_83xx_quad_entry {
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__le32 dr_addr;
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__le32 dr_value;
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__le32 ar_addr;
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__le32 ar_value;
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} __packed;
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struct qla4_83xx_reset_template {
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int seq_index;
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int seq_error;
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int array_index;
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uint32_t array[QLA83XX_MAX_RESET_SEQ_ENTRIES];
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uint8_t *buff;
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uint8_t *stop_offset;
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uint8_t *start_offset;
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uint8_t *init_offset;
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struct qla4_83xx_reset_template_hdr *hdr;
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uint8_t seq_end;
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uint8_t template_end;
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};
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/* POLLRD Entry */
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struct qla83xx_minidump_entry_pollrd {
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struct qla8xxx_minidump_entry_hdr h;
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uint32_t select_addr;
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uint32_t read_addr;
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uint32_t select_value;
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uint16_t select_value_stride;
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uint16_t op_count;
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uint32_t poll_wait;
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uint32_t poll_mask;
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uint32_t data_size;
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uint32_t rsvd_1;
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};
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struct qla8044_minidump_entry_rddfe {
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struct qla8xxx_minidump_entry_hdr h;
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uint32_t addr_1;
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uint32_t value;
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uint8_t stride;
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uint8_t stride2;
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uint16_t count;
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uint32_t poll;
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uint32_t mask;
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uint32_t modify_mask;
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uint32_t data_size;
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uint32_t rsvd;
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} __packed;
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struct qla8044_minidump_entry_rdmdio {
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struct qla8xxx_minidump_entry_hdr h;
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uint32_t addr_1;
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uint32_t addr_2;
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uint32_t value_1;
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uint8_t stride_1;
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uint8_t stride_2;
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uint16_t count;
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uint32_t poll;
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uint32_t mask;
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uint32_t value_2;
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uint32_t data_size;
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} __packed;
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struct qla8044_minidump_entry_pollwr {
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struct qla8xxx_minidump_entry_hdr h;
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uint32_t addr_1;
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uint32_t addr_2;
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uint32_t value_1;
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uint32_t value_2;
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uint32_t poll;
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uint32_t mask;
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uint32_t data_size;
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uint32_t rsvd;
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} __packed;
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/* RDMUX2 Entry */
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struct qla83xx_minidump_entry_rdmux2 {
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struct qla8xxx_minidump_entry_hdr h;
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uint32_t select_addr_1;
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uint32_t select_addr_2;
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uint32_t select_value_1;
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uint32_t select_value_2;
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uint32_t op_count;
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uint32_t select_value_mask;
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uint32_t read_addr;
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uint8_t select_value_stride;
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uint8_t data_size;
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uint8_t rsvd[2];
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};
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/* POLLRDMWR Entry */
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struct qla83xx_minidump_entry_pollrdmwr {
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struct qla8xxx_minidump_entry_hdr h;
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uint32_t addr_1;
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uint32_t addr_2;
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uint32_t value_1;
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uint32_t value_2;
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uint32_t poll_wait;
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uint32_t poll_mask;
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uint32_t modify_mask;
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uint32_t data_size;
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};
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/* IDC additional information */
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struct qla4_83xx_idc_information {
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uint32_t request_desc; /* IDC request descriptor */
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uint32_t info1; /* IDC additional info */
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uint32_t info2; /* IDC additional info */
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uint32_t info3; /* IDC additional info */
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};
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#define QLA83XX_PEX_DMA_ENGINE_INDEX 8
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#define QLA83XX_PEX_DMA_BASE_ADDRESS 0x77320000
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#define QLA83XX_PEX_DMA_NUM_OFFSET 0x10000
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#define QLA83XX_PEX_DMA_CMD_ADDR_LOW 0x0
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#define QLA83XX_PEX_DMA_CMD_ADDR_HIGH 0x04
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#define QLA83XX_PEX_DMA_CMD_STS_AND_CNTRL 0x08
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#define QLA83XX_PEX_DMA_READ_SIZE (16 * 1024)
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#define QLA83XX_PEX_DMA_MAX_WAIT (100 * 100) /* Max wait of 100 msecs */
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/* Read Memory: For Pex-DMA */
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struct qla4_83xx_minidump_entry_rdmem_pex_dma {
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struct qla8xxx_minidump_entry_hdr h;
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uint32_t desc_card_addr;
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uint16_t dma_desc_cmd;
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uint8_t rsvd[2];
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uint32_t start_dma_cmd;
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uint8_t rsvd2[12];
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uint32_t read_addr;
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uint32_t read_data_size;
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};
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struct qla4_83xx_pex_dma_descriptor {
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struct {
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uint32_t read_data_size; /* 0-23: size, 24-31: rsvd */
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uint8_t rsvd[2];
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uint16_t dma_desc_cmd;
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} cmd;
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uint64_t src_addr;
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uint64_t dma_bus_addr; /* 0-3: desc-cmd, 4-7: pci-func,
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* 8-15: desc-cmd */
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uint8_t rsvd[24];
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} __packed;
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#endif
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