96 lines
3.5 KiB
C
96 lines
3.5 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __SOC_MEDIATEK_MT8173_MMSYS_H
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#define __SOC_MEDIATEK_MT8173_MMSYS_H
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#define MT8173_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN 0x040
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#define MT8173_DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044
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#define MT8173_DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048
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#define MT8173_DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c
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#define MT8173_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050
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#define MT8173_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084
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#define MT8173_DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088
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#define MT8173_DISP_REG_CONFIG_DISP_AAL_SEL_IN 0x08c
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#define MT8173_DISP_REG_CONFIG_DISP_UFOE_SEL_IN 0x0a0
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#define MT8173_DISP_REG_CONFIG_DSI0_SEL_IN 0x0a4
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#define MT8173_DISP_REG_CONFIG_DPI_SEL_IN 0x0ac
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#define MT8173_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN 0x0b0
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#define MT8173_DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN 0x0c8
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#define MT8173_DISP_REG_CONFIG_DISP_COLOR0_SOUT_SEL_IN 0x0bc
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#define MT8173_AAL_SEL_IN_MERGE BIT(0)
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#define MT8173_COLOR0_SEL_IN_OVL0 BIT(0)
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#define MT8173_COLOR0_SOUT_MERGE BIT(0)
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#define MT8173_DPI0_SEL_IN_MASK GENMASK(1, 0)
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#define MT8173_DPI0_SEL_IN_RDMA1 BIT(0)
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#define MT8173_DSI0_SEL_IN_UFOE BIT(0)
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#define MT8173_GAMMA_MOUT_EN_RDMA1 BIT(0)
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#define MT8173_OD0_MOUT_EN_RDMA0 BIT(0)
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#define MT8173_OVL0_MOUT_EN_COLOR0 BIT(0)
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#define MT8173_OVL1_MOUT_EN_COLOR1 BIT(0)
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#define MT8173_UFOE_MOUT_EN_DSI0 BIT(0)
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#define MT8173_UFOE_SEL_IN_RDMA0 BIT(0)
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#define MT8173_RDMA0_SOUT_COLOR0 BIT(0)
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static const struct mtk_mmsys_routes mt8173_mmsys_routing_table[] = {
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{
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DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
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MT8173_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
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MT8173_OVL0_MOUT_EN_COLOR0, MT8173_OVL0_MOUT_EN_COLOR0
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}, {
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DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0,
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MT8173_DISP_REG_CONFIG_DISP_OD_MOUT_EN,
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MT8173_OD0_MOUT_EN_RDMA0, MT8173_OD0_MOUT_EN_RDMA0
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}, {
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DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,
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MT8173_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN,
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MT8173_UFOE_MOUT_EN_DSI0, MT8173_UFOE_MOUT_EN_DSI0
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}, {
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DDP_COMPONENT_COLOR0, DDP_COMPONENT_AAL0,
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MT8173_DISP_REG_CONFIG_DISP_COLOR0_SOUT_SEL_IN,
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MT8173_COLOR0_SOUT_MERGE, 0 /* SOUT to AAL */
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}, {
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_UFOE,
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MT8173_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN,
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MT8173_RDMA0_SOUT_COLOR0, 0 /* SOUT to UFOE */
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}, {
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DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
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MT8173_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
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MT8173_COLOR0_SEL_IN_OVL0, MT8173_COLOR0_SEL_IN_OVL0
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}, {
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DDP_COMPONENT_AAL0, DDP_COMPONENT_COLOR0,
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MT8173_DISP_REG_CONFIG_DISP_AAL_SEL_IN,
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MT8173_AAL_SEL_IN_MERGE, 0 /* SEL_IN from COLOR0 */
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}, {
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DDP_COMPONENT_RDMA0, DDP_COMPONENT_UFOE,
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MT8173_DISP_REG_CONFIG_DISP_UFOE_SEL_IN,
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MT8173_UFOE_SEL_IN_RDMA0, 0 /* SEL_IN from RDMA0 */
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}, {
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DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,
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MT8173_DISP_REG_CONFIG_DSI0_SEL_IN,
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MT8173_DSI0_SEL_IN_UFOE, 0, /* SEL_IN from UFOE */
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}, {
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DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
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MT8173_DISP_REG_CONFIG_DISP_OVL1_MOUT_EN,
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MT8173_OVL1_MOUT_EN_COLOR1, MT8173_OVL1_MOUT_EN_COLOR1
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}, {
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DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1,
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MT8173_DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN,
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MT8173_GAMMA_MOUT_EN_RDMA1, MT8173_GAMMA_MOUT_EN_RDMA1
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
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MT8173_DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN,
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RDMA1_SOUT_MASK, RDMA1_SOUT_DPI0
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}, {
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DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
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MT8173_DISP_REG_CONFIG_DISP_COLOR1_SEL_IN,
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COLOR1_SEL_IN_OVL1, COLOR1_SEL_IN_OVL1
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}, {
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DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
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MT8173_DISP_REG_CONFIG_DPI_SEL_IN,
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MT8173_DPI0_SEL_IN_MASK, MT8173_DPI0_SEL_IN_RDMA1
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}
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};
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#endif /* __SOC_MEDIATEK_MT8173_MMSYS_H */
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