219 lines
6.6 KiB
C
219 lines
6.6 KiB
C
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (C) 2022 Kernkonzept GmbH.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_8909_H
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#define _DT_BINDINGS_CLK_QCOM_GCC_8909_H
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/* PLLs */
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#define GPLL0_EARLY 0
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#define GPLL0 1
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#define GPLL1 2
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#define GPLL1_VOTE 3
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#define GPLL2_EARLY 4
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#define GPLL2 5
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#define BIMC_PLL_EARLY 6
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#define BIMC_PLL 7
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/* RCGs */
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#define APSS_AHB_CLK_SRC 8
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#define BIMC_DDR_CLK_SRC 9
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#define BIMC_GPU_CLK_SRC 10
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#define BLSP1_QUP1_I2C_APPS_CLK_SRC 11
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#define BLSP1_QUP1_SPI_APPS_CLK_SRC 12
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#define BLSP1_QUP2_I2C_APPS_CLK_SRC 13
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#define BLSP1_QUP2_SPI_APPS_CLK_SRC 14
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#define BLSP1_QUP3_I2C_APPS_CLK_SRC 15
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#define BLSP1_QUP3_SPI_APPS_CLK_SRC 16
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#define BLSP1_QUP4_I2C_APPS_CLK_SRC 17
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#define BLSP1_QUP4_SPI_APPS_CLK_SRC 18
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#define BLSP1_QUP5_I2C_APPS_CLK_SRC 19
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#define BLSP1_QUP5_SPI_APPS_CLK_SRC 20
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#define BLSP1_QUP6_I2C_APPS_CLK_SRC 21
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#define BLSP1_QUP6_SPI_APPS_CLK_SRC 22
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#define BLSP1_UART1_APPS_CLK_SRC 23
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#define BLSP1_UART2_APPS_CLK_SRC 24
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#define BYTE0_CLK_SRC 25
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#define CAMSS_GP0_CLK_SRC 26
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#define CAMSS_GP1_CLK_SRC 27
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#define CAMSS_TOP_AHB_CLK_SRC 28
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#define CODEC_DIGCODEC_CLK_SRC 29
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#define CRYPTO_CLK_SRC 30
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#define CSI0_CLK_SRC 31
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#define CSI0PHYTIMER_CLK_SRC 32
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#define CSI1_CLK_SRC 33
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#define ESC0_CLK_SRC 34
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#define GFX3D_CLK_SRC 35
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#define GP1_CLK_SRC 36
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#define GP2_CLK_SRC 37
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#define GP3_CLK_SRC 38
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#define MCLK0_CLK_SRC 39
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#define MCLK1_CLK_SRC 40
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#define MDP_CLK_SRC 41
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#define PCLK0_CLK_SRC 42
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#define PCNOC_BFDCD_CLK_SRC 43
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#define PDM2_CLK_SRC 44
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#define SDCC1_APPS_CLK_SRC 45
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#define SDCC2_APPS_CLK_SRC 46
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#define SYSTEM_NOC_BFDCD_CLK_SRC 47
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#define ULTAUDIO_AHBFABRIC_CLK_SRC 48
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#define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC 49
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#define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC 50
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#define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC 51
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#define ULTAUDIO_XO_CLK_SRC 52
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#define USB_HS_SYSTEM_CLK_SRC 53
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#define VCODEC0_CLK_SRC 54
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#define VFE0_CLK_SRC 55
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#define VSYNC_CLK_SRC 56
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/* Voteable Clocks */
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#define GCC_APSS_TCU_CLK 57
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#define GCC_BLSP1_AHB_CLK 58
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#define GCC_BLSP1_SLEEP_CLK 59
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#define GCC_BOOT_ROM_AHB_CLK 60
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#define GCC_CRYPTO_CLK 61
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#define GCC_CRYPTO_AHB_CLK 62
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#define GCC_CRYPTO_AXI_CLK 63
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#define GCC_GFX_TBU_CLK 64
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#define GCC_GFX_TCU_CLK 65
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#define GCC_GTCU_AHB_CLK 66
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#define GCC_MDP_TBU_CLK 67
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#define GCC_PRNG_AHB_CLK 68
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#define GCC_SMMU_CFG_CLK 69
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#define GCC_VENUS_TBU_CLK 70
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#define GCC_VFE_TBU_CLK 71
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/* Branches */
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#define GCC_BIMC_GFX_CLK 72
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#define GCC_BIMC_GPU_CLK 73
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#define GCC_BLSP1_QUP1_I2C_APPS_CLK 74
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#define GCC_BLSP1_QUP1_SPI_APPS_CLK 75
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#define GCC_BLSP1_QUP2_I2C_APPS_CLK 76
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#define GCC_BLSP1_QUP2_SPI_APPS_CLK 77
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#define GCC_BLSP1_QUP3_I2C_APPS_CLK 78
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#define GCC_BLSP1_QUP3_SPI_APPS_CLK 79
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#define GCC_BLSP1_QUP4_I2C_APPS_CLK 80
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#define GCC_BLSP1_QUP4_SPI_APPS_CLK 81
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#define GCC_BLSP1_QUP5_I2C_APPS_CLK 82
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#define GCC_BLSP1_QUP5_SPI_APPS_CLK 83
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#define GCC_BLSP1_QUP6_I2C_APPS_CLK 84
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#define GCC_BLSP1_QUP6_SPI_APPS_CLK 85
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#define GCC_BLSP1_UART1_APPS_CLK 86
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#define GCC_BLSP1_UART2_APPS_CLK 87
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#define GCC_CAMSS_AHB_CLK 88
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#define GCC_CAMSS_CSI0_CLK 89
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#define GCC_CAMSS_CSI0_AHB_CLK 90
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#define GCC_CAMSS_CSI0PHY_CLK 91
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#define GCC_CAMSS_CSI0PHYTIMER_CLK 92
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#define GCC_CAMSS_CSI0PIX_CLK 93
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#define GCC_CAMSS_CSI0RDI_CLK 94
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#define GCC_CAMSS_CSI1_CLK 95
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#define GCC_CAMSS_CSI1_AHB_CLK 96
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#define GCC_CAMSS_CSI1PHY_CLK 97
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#define GCC_CAMSS_CSI1PIX_CLK 98
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#define GCC_CAMSS_CSI1RDI_CLK 99
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#define GCC_CAMSS_CSI_VFE0_CLK 100
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#define GCC_CAMSS_GP0_CLK 101
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#define GCC_CAMSS_GP1_CLK 102
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#define GCC_CAMSS_ISPIF_AHB_CLK 103
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#define GCC_CAMSS_MCLK0_CLK 104
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#define GCC_CAMSS_MCLK1_CLK 105
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#define GCC_CAMSS_TOP_AHB_CLK 106
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#define GCC_CAMSS_VFE0_CLK 107
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#define GCC_CAMSS_VFE_AHB_CLK 108
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#define GCC_CAMSS_VFE_AXI_CLK 109
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#define GCC_CODEC_DIGCODEC_CLK 110
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#define GCC_GP1_CLK 111
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#define GCC_GP2_CLK 112
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#define GCC_GP3_CLK 113
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#define GCC_MDSS_AHB_CLK 114
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#define GCC_MDSS_AXI_CLK 115
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#define GCC_MDSS_BYTE0_CLK 116
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#define GCC_MDSS_ESC0_CLK 117
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#define GCC_MDSS_MDP_CLK 118
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#define GCC_MDSS_PCLK0_CLK 119
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#define GCC_MDSS_VSYNC_CLK 120
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#define GCC_MSS_CFG_AHB_CLK 121
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#define GCC_MSS_Q6_BIMC_AXI_CLK 122
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#define GCC_OXILI_AHB_CLK 123
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#define GCC_OXILI_GFX3D_CLK 124
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#define GCC_PDM2_CLK 125
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#define GCC_PDM_AHB_CLK 126
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#define GCC_SDCC1_AHB_CLK 127
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#define GCC_SDCC1_APPS_CLK 128
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#define GCC_SDCC2_AHB_CLK 129
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#define GCC_SDCC2_APPS_CLK 130
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#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK 131
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#define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK 132
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#define GCC_ULTAUDIO_AVSYNC_XO_CLK 133
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#define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK 134
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#define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK 135
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#define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK 136
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#define GCC_ULTAUDIO_PCNOC_MPORT_CLK 137
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#define GCC_ULTAUDIO_PCNOC_SWAY_CLK 138
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#define GCC_ULTAUDIO_STC_XO_CLK 139
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#define GCC_USB2A_PHY_SLEEP_CLK 140
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#define GCC_USB_HS_AHB_CLK 141
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#define GCC_USB_HS_PHY_CFG_AHB_CLK 142
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#define GCC_USB_HS_SYSTEM_CLK 143
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#define GCC_VENUS0_AHB_CLK 144
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#define GCC_VENUS0_AXI_CLK 145
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#define GCC_VENUS0_CORE0_VCODEC0_CLK 146
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#define GCC_VENUS0_VCODEC0_CLK 147
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/* Resets */
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#define GCC_AUDIO_CORE_BCR 0
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#define GCC_BLSP1_BCR 1
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#define GCC_BLSP1_QUP1_BCR 2
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#define GCC_BLSP1_QUP2_BCR 3
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#define GCC_BLSP1_QUP3_BCR 4
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#define GCC_BLSP1_QUP4_BCR 5
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#define GCC_BLSP1_QUP5_BCR 6
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#define GCC_BLSP1_QUP6_BCR 7
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#define GCC_BLSP1_UART1_BCR 8
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#define GCC_BLSP1_UART2_BCR 9
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#define GCC_CAMSS_CSI0_BCR 10
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#define GCC_CAMSS_CSI0PHY_BCR 11
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#define GCC_CAMSS_CSI0PIX_BCR 12
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#define GCC_CAMSS_CSI0RDI_BCR 13
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#define GCC_CAMSS_CSI1_BCR 14
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#define GCC_CAMSS_CSI1PHY_BCR 15
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#define GCC_CAMSS_CSI1PIX_BCR 16
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#define GCC_CAMSS_CSI1RDI_BCR 17
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#define GCC_CAMSS_CSI_VFE0_BCR 18
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#define GCC_CAMSS_GP0_BCR 19
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#define GCC_CAMSS_GP1_BCR 20
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#define GCC_CAMSS_ISPIF_BCR 21
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#define GCC_CAMSS_MCLK0_BCR 22
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#define GCC_CAMSS_MCLK1_BCR 23
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#define GCC_CAMSS_PHY0_BCR 24
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#define GCC_CAMSS_TOP_BCR 25
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#define GCC_CAMSS_TOP_AHB_BCR 26
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#define GCC_CAMSS_VFE_BCR 27
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#define GCC_CRYPTO_BCR 28
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#define GCC_MDSS_BCR 29
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#define GCC_OXILI_BCR 30
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#define GCC_PDM_BCR 31
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#define GCC_PRNG_BCR 32
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#define GCC_QUSB2_PHY_BCR 33
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#define GCC_SDCC1_BCR 34
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#define GCC_SDCC2_BCR 35
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#define GCC_ULT_AUDIO_BCR 36
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#define GCC_USB2A_PHY_BCR 37
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#define GCC_USB2_HS_PHY_ONLY_BCR 38
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#define GCC_USB_HS_BCR 39
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#define GCC_VENUS0_BCR 40
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/* Subsystem Restart */
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#define GCC_MSS_RESTART 41
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/* Power Domains */
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#define MDSS_GDSC 0
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#define OXILI_GDSC 1
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#define VENUS_GDSC 2
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#define VENUS_CORE0_GDSC 3
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#define VFE_GDSC 4
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#endif
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