187 lines
6.5 KiB
C
187 lines
6.5 KiB
C
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
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* Copyright (c) 2023, Danila Tikhonov <danila@jiaxyga.com>
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* Copyright (c) 2023, David Wronek <davidwronek@gmail.com>
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM7150_H
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#define _DT_BINDINGS_CLK_QCOM_GCC_SM7150_H
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/* GCC clock registers */
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#define GCC_GPLL0_MAIN_DIV_CDIV 0
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#define GPLL0 1
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#define GPLL0_OUT_EVEN 2
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#define GPLL6 3
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#define GPLL7 4
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#define GCC_AGGRE_NOC_PCIE_TBU_CLK 5
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#define GCC_AGGRE_UFS_PHY_AXI_CLK 6
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#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 7
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#define GCC_AGGRE_USB3_PRIM_AXI_CLK 8
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#define GCC_APC_VS_CLK 9
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#define GCC_BOOT_ROM_AHB_CLK 10
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#define GCC_CAMERA_HF_AXI_CLK 11
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#define GCC_CAMERA_SF_AXI_CLK 12
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#define GCC_CE1_AHB_CLK 13
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#define GCC_CE1_AXI_CLK 14
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#define GCC_CE1_CLK 15
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#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 16
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#define GCC_CPUSS_AHB_CLK 17
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#define GCC_CPUSS_AHB_CLK_SRC 18
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#define GCC_CPUSS_RBCPR_CLK 19
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#define GCC_CPUSS_RBCPR_CLK_SRC 20
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#define GCC_DDRSS_GPU_AXI_CLK 21
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#define GCC_DISP_GPLL0_CLK_SRC 22
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#define GCC_DISP_GPLL0_DIV_CLK_SRC 23
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#define GCC_DISP_HF_AXI_CLK 24
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#define GCC_DISP_SF_AXI_CLK 25
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#define GCC_GP1_CLK 26
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#define GCC_GP1_CLK_SRC 27
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#define GCC_GP2_CLK 28
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#define GCC_GP2_CLK_SRC 29
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#define GCC_GP3_CLK 30
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#define GCC_GP3_CLK_SRC 31
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#define GCC_GPU_GPLL0_CLK_SRC 32
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#define GCC_GPU_GPLL0_DIV_CLK_SRC 33
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#define GCC_GPU_MEMNOC_GFX_CLK 34
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#define GCC_GPU_SNOC_DVM_GFX_CLK 35
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#define GCC_GPU_VS_CLK 36
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#define GCC_NPU_AXI_CLK 37
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#define GCC_NPU_CFG_AHB_CLK 38
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#define GCC_NPU_GPLL0_CLK_SRC 39
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#define GCC_NPU_GPLL0_DIV_CLK_SRC 40
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#define GCC_PCIE_0_AUX_CLK 41
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#define GCC_PCIE_0_AUX_CLK_SRC 42
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#define GCC_PCIE_0_CFG_AHB_CLK 43
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#define GCC_PCIE_0_CLKREF_CLK 44
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#define GCC_PCIE_0_MSTR_AXI_CLK 45
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#define GCC_PCIE_0_PIPE_CLK 46
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#define GCC_PCIE_0_SLV_AXI_CLK 47
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#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48
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#define GCC_PCIE_PHY_AUX_CLK 49
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#define GCC_PCIE_PHY_REFGEN_CLK 50
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#define GCC_PCIE_PHY_REFGEN_CLK_SRC 51
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#define GCC_PDM2_CLK 52
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#define GCC_PDM2_CLK_SRC 53
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#define GCC_PDM_AHB_CLK 54
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#define GCC_PDM_XO4_CLK 55
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#define GCC_PRNG_AHB_CLK 56
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#define GCC_QUPV3_WRAP0_CORE_2X_CLK 57
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#define GCC_QUPV3_WRAP0_CORE_CLK 58
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#define GCC_QUPV3_WRAP0_S0_CLK 59
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#define GCC_QUPV3_WRAP0_S0_CLK_SRC 60
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#define GCC_QUPV3_WRAP0_S1_CLK 61
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#define GCC_QUPV3_WRAP0_S1_CLK_SRC 62
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#define GCC_QUPV3_WRAP0_S2_CLK 63
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#define GCC_QUPV3_WRAP0_S2_CLK_SRC 64
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#define GCC_QUPV3_WRAP0_S3_CLK 65
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#define GCC_QUPV3_WRAP0_S3_CLK_SRC 66
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#define GCC_QUPV3_WRAP0_S4_CLK 67
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#define GCC_QUPV3_WRAP0_S4_CLK_SRC 68
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#define GCC_QUPV3_WRAP0_S5_CLK 69
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#define GCC_QUPV3_WRAP0_S5_CLK_SRC 70
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#define GCC_QUPV3_WRAP0_S6_CLK 71
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#define GCC_QUPV3_WRAP0_S6_CLK_SRC 72
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#define GCC_QUPV3_WRAP0_S7_CLK 73
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#define GCC_QUPV3_WRAP0_S7_CLK_SRC 74
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#define GCC_QUPV3_WRAP1_CORE_2X_CLK 75
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#define GCC_QUPV3_WRAP1_CORE_CLK 76
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#define GCC_QUPV3_WRAP1_S0_CLK 77
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#define GCC_QUPV3_WRAP1_S0_CLK_SRC 78
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#define GCC_QUPV3_WRAP1_S1_CLK 79
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#define GCC_QUPV3_WRAP1_S1_CLK_SRC 80
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#define GCC_QUPV3_WRAP1_S2_CLK 81
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#define GCC_QUPV3_WRAP1_S2_CLK_SRC 82
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#define GCC_QUPV3_WRAP1_S3_CLK 83
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#define GCC_QUPV3_WRAP1_S3_CLK_SRC 84
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#define GCC_QUPV3_WRAP1_S4_CLK 85
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#define GCC_QUPV3_WRAP1_S4_CLK_SRC 86
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#define GCC_QUPV3_WRAP1_S5_CLK 87
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#define GCC_QUPV3_WRAP1_S5_CLK_SRC 88
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#define GCC_QUPV3_WRAP1_S6_CLK 89
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#define GCC_QUPV3_WRAP1_S6_CLK_SRC 90
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#define GCC_QUPV3_WRAP1_S7_CLK 91
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#define GCC_QUPV3_WRAP1_S7_CLK_SRC 92
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#define GCC_QUPV3_WRAP_0_M_AHB_CLK 93
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#define GCC_QUPV3_WRAP_0_S_AHB_CLK 94
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#define GCC_QUPV3_WRAP_1_M_AHB_CLK 95
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#define GCC_QUPV3_WRAP_1_S_AHB_CLK 96
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#define GCC_SDCC1_AHB_CLK 97
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#define GCC_SDCC1_APPS_CLK 98
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#define GCC_SDCC1_APPS_CLK_SRC 99
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#define GCC_SDCC1_ICE_CORE_CLK 100
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#define GCC_SDCC1_ICE_CORE_CLK_SRC 101
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#define GCC_SDCC2_AHB_CLK 102
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#define GCC_SDCC2_APPS_CLK 103
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#define GCC_SDCC2_APPS_CLK_SRC 104
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#define GCC_SDCC4_AHB_CLK 105
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#define GCC_SDCC4_APPS_CLK 106
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#define GCC_SDCC4_APPS_CLK_SRC 107
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#define GCC_SYS_NOC_CPUSS_AHB_CLK 108
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#define GCC_TSIF_AHB_CLK 109
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#define GCC_TSIF_INACTIVITY_TIMERS_CLK 110
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#define GCC_TSIF_REF_CLK 111
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#define GCC_TSIF_REF_CLK_SRC 112
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#define GCC_UFS_MEM_CLKREF_CLK 113
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#define GCC_UFS_PHY_AHB_CLK 114
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#define GCC_UFS_PHY_AXI_CLK 115
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#define GCC_UFS_PHY_AXI_CLK_SRC 116
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#define GCC_UFS_PHY_AXI_HW_CTL_CLK 117
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#define GCC_UFS_PHY_ICE_CORE_CLK 118
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#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 119
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#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 120
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#define GCC_UFS_PHY_PHY_AUX_CLK 121
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#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 122
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#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 123
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 124
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 125
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK 126
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 127
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#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 128
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#define GCC_USB30_PRIM_MASTER_CLK 129
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#define GCC_USB30_PRIM_MASTER_CLK_SRC 130
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK 131
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 132
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#define GCC_USB30_PRIM_SLEEP_CLK 133
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#define GCC_USB3_PRIM_CLKREF_CLK 134
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#define GCC_USB3_PRIM_PHY_AUX_CLK 135
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#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 136
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#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 137
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#define GCC_USB3_PRIM_PHY_PIPE_CLK 138
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#define GCC_USB_PHY_CFG_AHB2PHY_CLK 139
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#define GCC_VDDA_VS_CLK 140
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#define GCC_VDDCX_VS_CLK 141
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#define GCC_VDDMX_VS_CLK 142
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#define GCC_VIDEO_AXI_CLK 143
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#define GCC_VS_CTRL_AHB_CLK 144
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#define GCC_VS_CTRL_CLK 145
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#define GCC_VS_CTRL_CLK_SRC 146
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#define GCC_VSENSOR_CLK_SRC 147
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/* GCC Resets */
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#define GCC_PCIE_0_BCR 0
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#define GCC_PCIE_PHY_BCR 1
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#define GCC_PCIE_PHY_COM_BCR 2
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#define GCC_UFS_PHY_BCR 3
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#define GCC_USB30_PRIM_BCR 4
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#define GCC_USB3_DP_PHY_PRIM_BCR 5
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#define GCC_USB3_DP_PHY_SEC_BCR 6
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#define GCC_USB3_PHY_PRIM_BCR 7
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#define GCC_USB3_PHY_SEC_BCR 8
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#define GCC_QUSB2PHY_PRIM_BCR 9
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#define GCC_VIDEO_AXI_CLK_BCR 10
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/* GCC GDSCRs */
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#define PCIE_0_GDSC 0
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#define UFS_PHY_GDSC 1
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#define USB30_PRIM_GDSC 2
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#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC 3
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#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC 4
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#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC 5
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#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC 6
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#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 7
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#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 8
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#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 9
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#endif
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