47 lines
1.6 KiB
C
47 lines
1.6 KiB
C
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/*
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* Copyright (c) 2021 MediaTek Inc.
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* Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_POWER_MT8195_POWER_H
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#define _DT_BINDINGS_POWER_MT8195_POWER_H
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#define MT8195_POWER_DOMAIN_PCIE_MAC_P0 0
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#define MT8195_POWER_DOMAIN_PCIE_MAC_P1 1
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#define MT8195_POWER_DOMAIN_PCIE_PHY 2
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#define MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY 3
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#define MT8195_POWER_DOMAIN_CSI_RX_TOP 4
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#define MT8195_POWER_DOMAIN_ETHER 5
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#define MT8195_POWER_DOMAIN_ADSP 6
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#define MT8195_POWER_DOMAIN_AUDIO 7
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#define MT8195_POWER_DOMAIN_MFG0 8
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#define MT8195_POWER_DOMAIN_MFG1 9
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#define MT8195_POWER_DOMAIN_MFG2 10
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#define MT8195_POWER_DOMAIN_MFG3 11
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#define MT8195_POWER_DOMAIN_MFG4 12
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#define MT8195_POWER_DOMAIN_MFG5 13
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#define MT8195_POWER_DOMAIN_MFG6 14
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#define MT8195_POWER_DOMAIN_VPPSYS0 15
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#define MT8195_POWER_DOMAIN_VDOSYS0 16
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#define MT8195_POWER_DOMAIN_VPPSYS1 17
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#define MT8195_POWER_DOMAIN_VDOSYS1 18
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#define MT8195_POWER_DOMAIN_DP_TX 19
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#define MT8195_POWER_DOMAIN_EPD_TX 20
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#define MT8195_POWER_DOMAIN_HDMI_TX 21
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#define MT8195_POWER_DOMAIN_WPESYS 22
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#define MT8195_POWER_DOMAIN_VDEC0 23
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#define MT8195_POWER_DOMAIN_VDEC1 24
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#define MT8195_POWER_DOMAIN_VDEC2 25
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#define MT8195_POWER_DOMAIN_VENC 26
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#define MT8195_POWER_DOMAIN_VENC_CORE1 27
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#define MT8195_POWER_DOMAIN_IMG 28
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#define MT8195_POWER_DOMAIN_DIP 29
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#define MT8195_POWER_DOMAIN_IPE 30
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#define MT8195_POWER_DOMAIN_CAM 31
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#define MT8195_POWER_DOMAIN_CAM_RAWA 32
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#define MT8195_POWER_DOMAIN_CAM_RAWB 33
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#define MT8195_POWER_DOMAIN_CAM_MRAW 34
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#endif /* _DT_BINDINGS_POWER_MT8195_POWER_H */
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