155 lines
5.2 KiB
C
155 lines
5.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 OR MIT */
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/*
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* Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
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*/
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#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__
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#define __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__
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/* SYSCRG resets */
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#define JH7110_SYSRST_JTAG_APB 0
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#define JH7110_SYSRST_SYSCON_APB 1
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#define JH7110_SYSRST_IOMUX_APB 2
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#define JH7110_SYSRST_BUS 3
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#define JH7110_SYSRST_DEBUG 4
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#define JH7110_SYSRST_CORE0 5
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#define JH7110_SYSRST_CORE1 6
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#define JH7110_SYSRST_CORE2 7
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#define JH7110_SYSRST_CORE3 8
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#define JH7110_SYSRST_CORE4 9
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#define JH7110_SYSRST_CORE0_ST 10
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#define JH7110_SYSRST_CORE1_ST 11
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#define JH7110_SYSRST_CORE2_ST 12
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#define JH7110_SYSRST_CORE3_ST 13
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#define JH7110_SYSRST_CORE4_ST 14
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#define JH7110_SYSRST_TRACE0 15
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#define JH7110_SYSRST_TRACE1 16
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#define JH7110_SYSRST_TRACE2 17
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#define JH7110_SYSRST_TRACE3 18
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#define JH7110_SYSRST_TRACE4 19
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#define JH7110_SYSRST_TRACE_COM 20
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#define JH7110_SYSRST_GPU_APB 21
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#define JH7110_SYSRST_GPU_DOMA 22
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#define JH7110_SYSRST_NOC_BUS_APB 23
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#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24
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#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25
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#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26
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#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27
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#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28
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#define JH7110_SYSRST_NOC_BUS_DDRC 29
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#define JH7110_SYSRST_NOC_BUS_STG_AXI 30
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#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31
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#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32
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#define JH7110_SYSRST_AXI_CFG1_AHB 33
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#define JH7110_SYSRST_AXI_CFG1_MAIN 34
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#define JH7110_SYSRST_AXI_CFG0_MAIN 35
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#define JH7110_SYSRST_AXI_CFG0_MAIN_DIV 36
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#define JH7110_SYSRST_AXI_CFG0_HIFI4 37
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#define JH7110_SYSRST_DDR_AXI 38
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#define JH7110_SYSRST_DDR_OSC 39
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#define JH7110_SYSRST_DDR_APB 40
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#define JH7110_SYSRST_ISP_TOP 41
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#define JH7110_SYSRST_ISP_TOP_AXI 42
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#define JH7110_SYSRST_VOUT_TOP_SRC 43
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#define JH7110_SYSRST_CODAJ12_AXI 44
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#define JH7110_SYSRST_CODAJ12_CORE 45
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#define JH7110_SYSRST_CODAJ12_APB 46
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#define JH7110_SYSRST_WAVE511_AXI 47
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#define JH7110_SYSRST_WAVE511_BPU 48
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#define JH7110_SYSRST_WAVE511_VCE 49
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#define JH7110_SYSRST_WAVE511_APB 50
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#define JH7110_SYSRST_VDEC_JPG 51
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#define JH7110_SYSRST_VDEC_MAIN 52
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#define JH7110_SYSRST_AXIMEM0_AXI 53
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#define JH7110_SYSRST_WAVE420L_AXI 54
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#define JH7110_SYSRST_WAVE420L_BPU 55
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#define JH7110_SYSRST_WAVE420L_VCE 56
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#define JH7110_SYSRST_WAVE420L_APB 57
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#define JH7110_SYSRST_AXIMEM1_AXI 58
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#define JH7110_SYSRST_AXIMEM2_AXI 59
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#define JH7110_SYSRST_INTMEM 60
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#define JH7110_SYSRST_QSPI_AHB 61
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#define JH7110_SYSRST_QSPI_APB 62
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#define JH7110_SYSRST_QSPI_REF 63
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#define JH7110_SYSRST_SDIO0_AHB 64
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#define JH7110_SYSRST_SDIO1_AHB 65
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#define JH7110_SYSRST_GMAC1_AXI 66
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#define JH7110_SYSRST_GMAC1_AHB 67
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#define JH7110_SYSRST_MAILBOX_APB 68
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#define JH7110_SYSRST_SPI0_APB 69
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#define JH7110_SYSRST_SPI1_APB 70
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#define JH7110_SYSRST_SPI2_APB 71
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#define JH7110_SYSRST_SPI3_APB 72
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#define JH7110_SYSRST_SPI4_APB 73
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#define JH7110_SYSRST_SPI5_APB 74
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#define JH7110_SYSRST_SPI6_APB 75
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#define JH7110_SYSRST_I2C0_APB 76
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#define JH7110_SYSRST_I2C1_APB 77
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#define JH7110_SYSRST_I2C2_APB 78
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#define JH7110_SYSRST_I2C3_APB 79
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#define JH7110_SYSRST_I2C4_APB 80
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#define JH7110_SYSRST_I2C5_APB 81
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#define JH7110_SYSRST_I2C6_APB 82
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#define JH7110_SYSRST_UART0_APB 83
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#define JH7110_SYSRST_UART0_CORE 84
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#define JH7110_SYSRST_UART1_APB 85
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#define JH7110_SYSRST_UART1_CORE 86
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#define JH7110_SYSRST_UART2_APB 87
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#define JH7110_SYSRST_UART2_CORE 88
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#define JH7110_SYSRST_UART3_APB 89
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#define JH7110_SYSRST_UART3_CORE 90
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#define JH7110_SYSRST_UART4_APB 91
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#define JH7110_SYSRST_UART4_CORE 92
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#define JH7110_SYSRST_UART5_APB 93
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#define JH7110_SYSRST_UART5_CORE 94
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#define JH7110_SYSRST_SPDIF_APB 95
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#define JH7110_SYSRST_PWMDAC_APB 96
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#define JH7110_SYSRST_PDM_DMIC 97
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#define JH7110_SYSRST_PDM_APB 98
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#define JH7110_SYSRST_I2SRX_APB 99
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#define JH7110_SYSRST_I2SRX_BCLK 100
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#define JH7110_SYSRST_I2STX0_APB 101
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#define JH7110_SYSRST_I2STX0_BCLK 102
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#define JH7110_SYSRST_I2STX1_APB 103
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#define JH7110_SYSRST_I2STX1_BCLK 104
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#define JH7110_SYSRST_TDM_AHB 105
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#define JH7110_SYSRST_TDM_CORE 106
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#define JH7110_SYSRST_TDM_APB 107
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#define JH7110_SYSRST_PWM_APB 108
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#define JH7110_SYSRST_WDT_APB 109
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#define JH7110_SYSRST_WDT_CORE 110
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#define JH7110_SYSRST_CAN0_APB 111
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#define JH7110_SYSRST_CAN0_CORE 112
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#define JH7110_SYSRST_CAN0_TIMER 113
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#define JH7110_SYSRST_CAN1_APB 114
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#define JH7110_SYSRST_CAN1_CORE 115
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#define JH7110_SYSRST_CAN1_TIMER 116
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#define JH7110_SYSRST_TIMER_APB 117
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#define JH7110_SYSRST_TIMER0 118
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#define JH7110_SYSRST_TIMER1 119
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#define JH7110_SYSRST_TIMER2 120
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#define JH7110_SYSRST_TIMER3 121
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#define JH7110_SYSRST_INT_CTRL_APB 122
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#define JH7110_SYSRST_TEMP_APB 123
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#define JH7110_SYSRST_TEMP_CORE 124
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#define JH7110_SYSRST_JTAG_CERTIFICATION 125
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#define JH7110_SYSRST_END 126
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/* AONCRG resets */
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#define JH7110_AONRST_GMAC0_AXI 0
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#define JH7110_AONRST_GMAC0_AHB 1
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#define JH7110_AONRST_IOMUX 2
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#define JH7110_AONRST_PMU_APB 3
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#define JH7110_AONRST_PMU_WKUP 4
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#define JH7110_AONRST_RTC_APB 5
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#define JH7110_AONRST_RTC_CAL 6
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#define JH7110_AONRST_RTC_32K 7
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#define JH7110_AONRST_END 8
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#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */
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