2023-08-30 17:31:07 +02:00
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* linux/include/linux/amd-pstate.h
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*
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* Copyright (C) 2022 Advanced Micro Devices, Inc.
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*
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* Author: Meng Li <li.meng@amd.com>
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*/
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#ifndef _LINUX_AMD_PSTATE_H
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#define _LINUX_AMD_PSTATE_H
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#include <linux/pm_qos.h>
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#define AMD_CPPC_EPP_PERFORMANCE 0x00
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#define AMD_CPPC_EPP_BALANCE_PERFORMANCE 0x80
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#define AMD_CPPC_EPP_BALANCE_POWERSAVE 0xBF
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#define AMD_CPPC_EPP_POWERSAVE 0xFF
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/*********************************************************************
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* AMD P-state INTERFACE *
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*********************************************************************/
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/**
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* struct amd_aperf_mperf
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* @aperf: actual performance frequency clock count
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* @mperf: maximum performance frequency clock count
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* @tsc: time stamp counter
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*/
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struct amd_aperf_mperf {
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u64 aperf;
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u64 mperf;
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u64 tsc;
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};
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/**
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* struct amd_cpudata - private CPU data for AMD P-State
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* @cpu: CPU number
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* @req: constraint request to apply
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* @cppc_req_cached: cached performance request hints
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* @highest_perf: the maximum performance an individual processor may reach,
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* assuming ideal conditions
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* @nominal_perf: the maximum sustained performance level of the processor,
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* assuming ideal operating conditions
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* @lowest_nonlinear_perf: the lowest performance level at which nonlinear power
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* savings are achieved
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* @lowest_perf: the absolute lowest performance level of the processor
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* @max_freq: the frequency that mapped to highest_perf
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* @min_freq: the frequency that mapped to lowest_perf
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* @nominal_freq: the frequency that mapped to nominal_perf
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* @lowest_nonlinear_freq: the frequency that mapped to lowest_nonlinear_perf
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* @cur: Difference of Aperf/Mperf/tsc count between last and current sample
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* @prev: Last Aperf/Mperf/tsc count value read from register
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* @freq: current cpu frequency value
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* @boost_supported: check whether the Processor or SBIOS supports boost mode
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* @epp_policy: Last saved policy used to set energy-performance preference
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* @epp_cached: Cached CPPC energy-performance preference value
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* @policy: Cpufreq policy value
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* @cppc_cap1_cached Cached MSR_AMD_CPPC_CAP1 register value
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*
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* The amd_cpudata is key private data for each CPU thread in AMD P-State, and
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* represents all the attributes and goals that AMD P-State requests at runtime.
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*/
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struct amd_cpudata {
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int cpu;
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struct freq_qos_request req[2];
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u64 cppc_req_cached;
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u32 highest_perf;
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u32 nominal_perf;
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u32 lowest_nonlinear_perf;
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u32 lowest_perf;
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u32 max_freq;
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u32 min_freq;
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u32 nominal_freq;
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u32 lowest_nonlinear_freq;
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struct amd_aperf_mperf cur;
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struct amd_aperf_mperf prev;
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u64 freq;
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bool boost_supported;
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/* EPP feature related attributes*/
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s16 epp_policy;
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s16 epp_cached;
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u32 policy;
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u64 cppc_cap1_cached;
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bool suspended;
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};
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/*
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* enum amd_pstate_mode - driver working mode of amd pstate
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*/
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enum amd_pstate_mode {
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2023-10-24 12:59:35 +02:00
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AMD_PSTATE_UNDEFINED = 0,
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AMD_PSTATE_DISABLE,
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2023-08-30 17:31:07 +02:00
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AMD_PSTATE_PASSIVE,
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AMD_PSTATE_ACTIVE,
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2023-10-24 12:59:35 +02:00
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AMD_PSTATE_GUIDED,
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2023-08-30 17:31:07 +02:00
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AMD_PSTATE_MAX,
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};
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static const char * const amd_pstate_mode_string[] = {
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2023-10-24 12:59:35 +02:00
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[AMD_PSTATE_UNDEFINED] = "undefined",
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2023-08-30 17:31:07 +02:00
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[AMD_PSTATE_DISABLE] = "disable",
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[AMD_PSTATE_PASSIVE] = "passive",
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[AMD_PSTATE_ACTIVE] = "active",
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2023-10-24 12:59:35 +02:00
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[AMD_PSTATE_GUIDED] = "guided",
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2023-08-30 17:31:07 +02:00
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NULL,
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};
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#endif /* _LINUX_AMD_PSTATE_H */
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