61 lines
1.9 KiB
C
61 lines
1.9 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright(C) 2015 Linaro Limited. All rights reserved.
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* Author: Mathieu Poirier <mathieu.poirier@linaro.org>
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*/
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#ifndef _LINUX_CORESIGHT_PMU_H
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#define _LINUX_CORESIGHT_PMU_H
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#include <linux/bits.h>
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#define CORESIGHT_ETM_PMU_NAME "cs_etm"
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/*
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* The legacy Trace ID system based on fixed calculation from the cpu
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* number. This has been replaced by drivers using a dynamic allocation
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* system - but need to retain the legacy algorithm for backward comparibility
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* in certain situations:-
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* a) new perf running on older systems that generate the legacy mapping
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* b) older tools that may not update at the same time as the kernel.
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*/
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#define CORESIGHT_LEGACY_CPU_TRACE_ID(cpu) (0x10 + (cpu * 2))
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/*
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* Below are the definition of bit offsets for perf option, and works as
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* arbitrary values for all ETM versions.
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*
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* Most of them are orignally from ETMv3.5/PTM's ETMCR config, therefore,
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* ETMv3.5/PTM doesn't define ETMCR config bits with prefix "ETM3_" and
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* directly use below macros as config bits.
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*/
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#define ETM_OPT_BRANCH_BROADCAST 8
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#define ETM_OPT_CYCACC 12
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#define ETM_OPT_CTXTID 14
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#define ETM_OPT_CTXTID2 15
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#define ETM_OPT_TS 28
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#define ETM_OPT_RETSTK 29
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/* ETMv4 CONFIGR programming bits for the ETM OPTs */
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#define ETM4_CFG_BIT_BB 3
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#define ETM4_CFG_BIT_CYCACC 4
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#define ETM4_CFG_BIT_CTXTID 6
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#define ETM4_CFG_BIT_VMID 7
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#define ETM4_CFG_BIT_TS 11
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#define ETM4_CFG_BIT_RETSTK 12
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#define ETM4_CFG_BIT_VMID_OPT 15
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/*
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* Interpretation of the PERF_RECORD_AUX_OUTPUT_HW_ID payload.
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* Used to associate a CPU with the CoreSight Trace ID.
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* [07:00] - Trace ID - uses 8 bits to make value easy to read in file.
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* [59:08] - Unused (SBZ)
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* [63:60] - Version
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*/
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#define CS_AUX_HW_ID_TRACE_ID_MASK GENMASK_ULL(7, 0)
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#define CS_AUX_HW_ID_VERSION_MASK GENMASK_ULL(63, 60)
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#define CS_AUX_HW_ID_CURR_VERSION 0
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#endif
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