2023-08-30 17:31:07 +02:00
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* Copyright 2020 NXP. */
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#ifndef __LINUX_REG_PCA9450_H__
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#define __LINUX_REG_PCA9450_H__
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#include <linux/regmap.h>
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enum pca9450_chip_type {
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PCA9450_TYPE_PCA9450A = 0,
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PCA9450_TYPE_PCA9450BC,
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PCA9450_TYPE_AMOUNT,
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};
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enum {
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PCA9450_BUCK1 = 0,
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PCA9450_BUCK2,
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PCA9450_BUCK3,
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PCA9450_BUCK4,
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PCA9450_BUCK5,
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PCA9450_BUCK6,
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PCA9450_LDO1,
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PCA9450_LDO2,
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PCA9450_LDO3,
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PCA9450_LDO4,
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PCA9450_LDO5,
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PCA9450_REGULATOR_CNT,
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};
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enum {
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PCA9450_DVS_LEVEL_RUN = 0,
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PCA9450_DVS_LEVEL_STANDBY,
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PCA9450_DVS_LEVEL_MAX,
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};
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#define PCA9450_BUCK1_VOLTAGE_NUM 0x80
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#define PCA9450_BUCK2_VOLTAGE_NUM 0x80
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#define PCA9450_BUCK3_VOLTAGE_NUM 0x80
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#define PCA9450_BUCK4_VOLTAGE_NUM 0x80
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#define PCA9450_BUCK5_VOLTAGE_NUM 0x80
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#define PCA9450_BUCK6_VOLTAGE_NUM 0x80
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#define PCA9450_LDO1_VOLTAGE_NUM 0x08
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#define PCA9450_LDO2_VOLTAGE_NUM 0x08
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#define PCA9450_LDO3_VOLTAGE_NUM 0x20
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#define PCA9450_LDO4_VOLTAGE_NUM 0x20
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#define PCA9450_LDO5_VOLTAGE_NUM 0x10
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enum {
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PCA9450_REG_DEV_ID = 0x00,
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PCA9450_REG_INT1 = 0x01,
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PCA9450_REG_INT1_MSK = 0x02,
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PCA9450_REG_STATUS1 = 0x03,
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PCA9450_REG_STATUS2 = 0x04,
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PCA9450_REG_PWRON_STAT = 0x05,
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PCA9450_REG_SWRST = 0x06,
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PCA9450_REG_PWRCTRL = 0x07,
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PCA9450_REG_RESET_CTRL = 0x08,
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PCA9450_REG_CONFIG1 = 0x09,
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PCA9450_REG_CONFIG2 = 0x0A,
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PCA9450_REG_BUCK123_DVS = 0x0C,
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PCA9450_REG_BUCK1OUT_LIMIT = 0x0D,
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PCA9450_REG_BUCK2OUT_LIMIT = 0x0E,
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PCA9450_REG_BUCK3OUT_LIMIT = 0x0F,
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PCA9450_REG_BUCK1CTRL = 0x10,
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PCA9450_REG_BUCK1OUT_DVS0 = 0x11,
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PCA9450_REG_BUCK1OUT_DVS1 = 0x12,
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PCA9450_REG_BUCK2CTRL = 0x13,
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PCA9450_REG_BUCK2OUT_DVS0 = 0x14,
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PCA9450_REG_BUCK2OUT_DVS1 = 0x15,
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PCA9450_REG_BUCK3CTRL = 0x16,
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PCA9450_REG_BUCK3OUT_DVS0 = 0x17,
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PCA9450_REG_BUCK3OUT_DVS1 = 0x18,
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PCA9450_REG_BUCK4CTRL = 0x19,
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PCA9450_REG_BUCK4OUT = 0x1A,
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PCA9450_REG_BUCK5CTRL = 0x1B,
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PCA9450_REG_BUCK5OUT = 0x1C,
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PCA9450_REG_BUCK6CTRL = 0x1D,
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PCA9450_REG_BUCK6OUT = 0x1E,
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PCA9450_REG_LDO_AD_CTRL = 0x20,
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PCA9450_REG_LDO1CTRL = 0x21,
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PCA9450_REG_LDO2CTRL = 0x22,
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PCA9450_REG_LDO3CTRL = 0x23,
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PCA9450_REG_LDO4CTRL = 0x24,
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PCA9450_REG_LDO5CTRL_L = 0x25,
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PCA9450_REG_LDO5CTRL_H = 0x26,
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PCA9450_REG_LOADSW_CTRL = 0x2A,
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PCA9450_REG_VRFLT1_STS = 0x2B,
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PCA9450_REG_VRFLT2_STS = 0x2C,
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PCA9450_REG_VRFLT1_MASK = 0x2D,
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PCA9450_REG_VRFLT2_MASK = 0x2E,
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PCA9450_MAX_REGISTER = 0x2F,
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};
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/* PCA9450 BUCK ENMODE bits */
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#define BUCK_ENMODE_OFF 0x00
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#define BUCK_ENMODE_ONREQ 0x01
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#define BUCK_ENMODE_ONREQ_STBYREQ 0x02
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#define BUCK_ENMODE_ON 0x03
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/* PCA9450_REG_BUCK1_CTRL bits */
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#define BUCK1_RAMP_MASK 0xC0
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#define BUCK1_RAMP_25MV 0x0
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#define BUCK1_RAMP_12P5MV 0x1
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#define BUCK1_RAMP_6P25MV 0x2
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#define BUCK1_RAMP_3P125MV 0x3
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#define BUCK1_DVS_CTRL 0x10
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#define BUCK1_AD 0x08
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#define BUCK1_FPWM 0x04
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#define BUCK1_ENMODE_MASK 0x03
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/* PCA9450_REG_BUCK2_CTRL bits */
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#define BUCK2_RAMP_MASK 0xC0
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#define BUCK2_RAMP_25MV 0x0
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#define BUCK2_RAMP_12P5MV 0x1
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#define BUCK2_RAMP_6P25MV 0x2
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#define BUCK2_RAMP_3P125MV 0x3
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#define BUCK2_DVS_CTRL 0x10
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#define BUCK2_AD 0x08
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#define BUCK2_FPWM 0x04
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#define BUCK2_ENMODE_MASK 0x03
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/* PCA9450_REG_BUCK3_CTRL bits */
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#define BUCK3_RAMP_MASK 0xC0
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#define BUCK3_RAMP_25MV 0x0
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#define BUCK3_RAMP_12P5MV 0x1
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#define BUCK3_RAMP_6P25MV 0x2
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#define BUCK3_RAMP_3P125MV 0x3
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#define BUCK3_DVS_CTRL 0x10
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#define BUCK3_AD 0x08
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#define BUCK3_FPWM 0x04
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#define BUCK3_ENMODE_MASK 0x03
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/* PCA9450_REG_BUCK4_CTRL bits */
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#define BUCK4_AD 0x08
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#define BUCK4_FPWM 0x04
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#define BUCK4_ENMODE_MASK 0x03
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/* PCA9450_REG_BUCK5_CTRL bits */
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#define BUCK5_AD 0x08
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#define BUCK5_FPWM 0x04
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#define BUCK5_ENMODE_MASK 0x03
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/* PCA9450_REG_BUCK6_CTRL bits */
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#define BUCK6_AD 0x08
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#define BUCK6_FPWM 0x04
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#define BUCK6_ENMODE_MASK 0x03
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/* PCA9450_REG_BUCK123_PRESET_EN bit */
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#define BUCK123_PRESET_EN 0x80
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/* PCA9450_BUCK1OUT_DVS0 bits */
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#define BUCK1OUT_DVS0_MASK 0x7F
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#define BUCK1OUT_DVS0_DEFAULT 0x14
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/* PCA9450_BUCK1OUT_DVS1 bits */
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#define BUCK1OUT_DVS1_MASK 0x7F
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#define BUCK1OUT_DVS1_DEFAULT 0x14
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/* PCA9450_BUCK2OUT_DVS0 bits */
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#define BUCK2OUT_DVS0_MASK 0x7F
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#define BUCK2OUT_DVS0_DEFAULT 0x14
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/* PCA9450_BUCK2OUT_DVS1 bits */
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#define BUCK2OUT_DVS1_MASK 0x7F
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#define BUCK2OUT_DVS1_DEFAULT 0x14
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/* PCA9450_BUCK3OUT_DVS0 bits */
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#define BUCK3OUT_DVS0_MASK 0x7F
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#define BUCK3OUT_DVS0_DEFAULT 0x14
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/* PCA9450_BUCK3OUT_DVS1 bits */
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#define BUCK3OUT_DVS1_MASK 0x7F
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#define BUCK3OUT_DVS1_DEFAULT 0x14
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/* PCA9450_REG_BUCK4OUT bits */
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#define BUCK4OUT_MASK 0x7F
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#define BUCK4OUT_DEFAULT 0x6C
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/* PCA9450_REG_BUCK5OUT bits */
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#define BUCK5OUT_MASK 0x7F
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#define BUCK5OUT_DEFAULT 0x30
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/* PCA9450_REG_BUCK6OUT bits */
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#define BUCK6OUT_MASK 0x7F
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#define BUCK6OUT_DEFAULT 0x14
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/* PCA9450_REG_LDO1_VOLT bits */
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#define LDO1_EN_MASK 0xC0
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#define LDO1OUT_MASK 0x07
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/* PCA9450_REG_LDO2_VOLT bits */
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#define LDO2_EN_MASK 0xC0
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#define LDO2OUT_MASK 0x07
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/* PCA9450_REG_LDO3_VOLT bits */
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#define LDO3_EN_MASK 0xC0
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#define LDO3OUT_MASK 0x1F
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2023-08-30 17:31:07 +02:00
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/* PCA9450_REG_LDO4_VOLT bits */
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#define LDO4_EN_MASK 0xC0
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#define LDO4OUT_MASK 0x1F
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2023-08-30 17:31:07 +02:00
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/* PCA9450_REG_LDO5_VOLT bits */
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#define LDO5L_EN_MASK 0xC0
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#define LDO5LOUT_MASK 0x0F
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#define LDO5H_EN_MASK 0xC0
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#define LDO5HOUT_MASK 0x0F
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/* PCA9450_REG_IRQ bits */
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#define IRQ_PWRON 0x80
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#define IRQ_WDOGB 0x40
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#define IRQ_RSVD 0x20
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#define IRQ_VR_FLT1 0x10
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#define IRQ_VR_FLT2 0x08
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#define IRQ_LOWVSYS 0x04
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#define IRQ_THERM_105 0x02
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#define IRQ_THERM_125 0x01
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/* PCA9450_REG_RESET_CTRL bits */
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#define WDOG_B_CFG_MASK 0xC0
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#define WDOG_B_CFG_NONE 0x00
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#define WDOG_B_CFG_WARM 0x40
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#define WDOG_B_CFG_COLD_LDO12 0x80
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#define WDOG_B_CFG_COLD 0xC0
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/* PCA9450_REG_CONFIG2 bits */
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#define I2C_LT_MASK 0x03
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#define I2C_LT_FORCE_DISABLE 0x00
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#define I2C_LT_ON_STANDBY_RUN 0x01
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#define I2C_LT_ON_RUN 0x02
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#define I2C_LT_FORCE_ENABLE 0x03
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#endif /* __LINUX_REG_PCA9450_H__ */
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