255 lines
7.2 KiB
C
255 lines
7.2 KiB
C
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/*
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* Copyright 2013 Red Hat
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef VIRTGPU_DRM_H
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#define VIRTGPU_DRM_H
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#include "drm.h"
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/* Please note that modifications to all structs defined here are
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* subject to backwards-compatibility constraints.
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*
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* Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel
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* compatibility Keep fields aligned to their size
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*/
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#define DRM_VIRTGPU_MAP 0x01
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#define DRM_VIRTGPU_EXECBUFFER 0x02
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#define DRM_VIRTGPU_GETPARAM 0x03
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#define DRM_VIRTGPU_RESOURCE_CREATE 0x04
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#define DRM_VIRTGPU_RESOURCE_INFO 0x05
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#define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06
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#define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07
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#define DRM_VIRTGPU_WAIT 0x08
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#define DRM_VIRTGPU_GET_CAPS 0x09
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#define DRM_VIRTGPU_RESOURCE_CREATE_BLOB 0x0a
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#define DRM_VIRTGPU_CONTEXT_INIT 0x0b
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#define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01
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#define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02
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#define VIRTGPU_EXECBUF_RING_IDX 0x04
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#define VIRTGPU_EXECBUF_FLAGS (\
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VIRTGPU_EXECBUF_FENCE_FD_IN |\
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VIRTGPU_EXECBUF_FENCE_FD_OUT |\
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VIRTGPU_EXECBUF_RING_IDX |\
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0)
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struct drm_virtgpu_map {
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__u64 offset; /* use for mmap system call */
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__u32 handle;
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__u32 pad;
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};
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/* fence_fd is modified on success if VIRTGPU_EXECBUF_FENCE_FD_OUT flag is set. */
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struct drm_virtgpu_execbuffer {
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__u32 flags;
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__u32 size;
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__u64 command; /* void* */
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__u64 bo_handles;
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__u32 num_bo_handles;
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__s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */
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__u32 ring_idx; /* command ring index (see VIRTGPU_EXECBUF_RING_IDX) */
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__u32 pad;
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};
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#define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */
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#define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 /* do we have the capset fix */
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#define VIRTGPU_PARAM_RESOURCE_BLOB 3 /* DRM_VIRTGPU_RESOURCE_CREATE_BLOB */
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#define VIRTGPU_PARAM_HOST_VISIBLE 4 /* Host blob resources are mappable */
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#define VIRTGPU_PARAM_CROSS_DEVICE 5 /* Cross virtio-device resource sharing */
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#define VIRTGPU_PARAM_CONTEXT_INIT 6 /* DRM_VIRTGPU_CONTEXT_INIT */
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#define VIRTGPU_PARAM_SUPPORTED_CAPSET_IDs 7 /* Bitmask of supported capability set ids */
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struct drm_virtgpu_getparam {
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__u64 param;
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__u64 value;
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};
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/* NO_BO flags? NO resource flag? */
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/* resource flag for y_0_top */
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struct drm_virtgpu_resource_create {
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__u32 target;
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__u32 format;
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__u32 bind;
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__u32 width;
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__u32 height;
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__u32 depth;
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__u32 array_size;
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__u32 last_level;
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__u32 nr_samples;
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__u32 flags;
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__u32 bo_handle; /* if this is set - recreate a new resource attached to this bo ? */
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__u32 res_handle; /* returned by kernel */
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__u32 size; /* validate transfer in the host */
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__u32 stride; /* validate transfer in the host */
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};
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struct drm_virtgpu_resource_info {
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__u32 bo_handle;
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__u32 res_handle;
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__u32 size;
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__u32 blob_mem;
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};
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struct drm_virtgpu_3d_box {
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__u32 x;
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__u32 y;
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__u32 z;
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__u32 w;
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__u32 h;
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__u32 d;
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};
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struct drm_virtgpu_3d_transfer_to_host {
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__u32 bo_handle;
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struct drm_virtgpu_3d_box box;
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__u32 level;
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__u32 offset;
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__u32 stride;
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__u32 layer_stride;
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};
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struct drm_virtgpu_3d_transfer_from_host {
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__u32 bo_handle;
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struct drm_virtgpu_3d_box box;
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__u32 level;
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__u32 offset;
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__u32 stride;
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__u32 layer_stride;
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};
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#define VIRTGPU_WAIT_NOWAIT 1 /* like it */
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struct drm_virtgpu_3d_wait {
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__u32 handle; /* 0 is an invalid handle */
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__u32 flags;
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};
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struct drm_virtgpu_get_caps {
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__u32 cap_set_id;
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__u32 cap_set_ver;
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__u64 addr;
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__u32 size;
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__u32 pad;
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};
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struct drm_virtgpu_resource_create_blob {
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#define VIRTGPU_BLOB_MEM_GUEST 0x0001
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#define VIRTGPU_BLOB_MEM_HOST3D 0x0002
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#define VIRTGPU_BLOB_MEM_HOST3D_GUEST 0x0003
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#define VIRTGPU_BLOB_FLAG_USE_MAPPABLE 0x0001
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#define VIRTGPU_BLOB_FLAG_USE_SHAREABLE 0x0002
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#define VIRTGPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004
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/* zero is invalid blob_mem */
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__u32 blob_mem;
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__u32 blob_flags;
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__u32 bo_handle;
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__u32 res_handle;
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__u64 size;
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/*
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* for 3D contexts with VIRTGPU_BLOB_MEM_HOST3D_GUEST and
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* VIRTGPU_BLOB_MEM_HOST3D otherwise, must be zero.
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*/
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__u32 pad;
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__u32 cmd_size;
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__u64 cmd;
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__u64 blob_id;
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};
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#define VIRTGPU_CONTEXT_PARAM_CAPSET_ID 0x0001
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#define VIRTGPU_CONTEXT_PARAM_NUM_RINGS 0x0002
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#define VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK 0x0003
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struct drm_virtgpu_context_set_param {
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__u64 param;
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__u64 value;
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};
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struct drm_virtgpu_context_init {
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__u32 num_params;
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__u32 pad;
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/* pointer to drm_virtgpu_context_set_param array */
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__u64 ctx_set_params;
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};
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/*
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* Event code that's given when VIRTGPU_CONTEXT_PARAM_POLL_RINGS_MASK is in
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* effect. The event size is sizeof(drm_event), since there is no additional
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* payload.
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*/
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#define VIRTGPU_EVENT_FENCE_SIGNALED 0x90000000
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#define DRM_IOCTL_VIRTGPU_MAP \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map)
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#define DRM_IOCTL_VIRTGPU_EXECBUFFER \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\
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struct drm_virtgpu_execbuffer)
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#define DRM_IOCTL_VIRTGPU_GETPARAM \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM,\
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struct drm_virtgpu_getparam)
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#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, \
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struct drm_virtgpu_resource_create)
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#define DRM_IOCTL_VIRTGPU_RESOURCE_INFO \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, \
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struct drm_virtgpu_resource_info)
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#define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, \
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struct drm_virtgpu_3d_transfer_from_host)
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#define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, \
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struct drm_virtgpu_3d_transfer_to_host)
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#define DRM_IOCTL_VIRTGPU_WAIT \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, \
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struct drm_virtgpu_3d_wait)
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#define DRM_IOCTL_VIRTGPU_GET_CAPS \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \
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struct drm_virtgpu_get_caps)
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#define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE_BLOB \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE_BLOB, \
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struct drm_virtgpu_resource_create_blob)
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#define DRM_IOCTL_VIRTGPU_CONTEXT_INIT \
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DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_CONTEXT_INIT, \
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struct drm_virtgpu_context_init)
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#if defined(__cplusplus)
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}
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#endif
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#endif
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