"BriefDescription":"Cycles when divider is busy executing divide operations",
"EventCode":"0x14",
"EventName":"ARITH.FPU_DIV_ACTIVE",
"PublicDescription":"This event counts the number of the divide operations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DIV_ACTIVE to get the number of the divide operations executed.",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Speculative and retired branches",
"EventCode":"0x88",
"EventName":"BR_INST_EXEC.ALL_BRANCHES",
"PublicDescription":"This event counts both taken and not taken speculative and retired branch instructions.",
"SampleAfterValue":"200003",
"UMask":"0xff"
},
{
"BriefDescription":"Speculative and retired macro-conditional branches",
"EventCode":"0x88",
"EventName":"BR_INST_EXEC.ALL_CONDITIONAL",
"PublicDescription":"This event counts both taken and not taken speculative and retired macro-conditional branch instructions.",
"SampleAfterValue":"200003",
"UMask":"0xc1"
},
{
"BriefDescription":"Speculative and retired macro-unconditional branches excluding calls and indirects",
"EventCode":"0x88",
"EventName":"BR_INST_EXEC.ALL_DIRECT_JMP",
"PublicDescription":"This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects.",
"SampleAfterValue":"200003",
"UMask":"0xc2"
},
{
"BriefDescription":"Speculative and retired direct near calls",
"EventCode":"0x88",
"EventName":"BR_INST_EXEC.ALL_DIRECT_NEAR_CALL",
"PublicDescription":"This event counts both taken and not taken speculative and retired direct near calls.",
"SampleAfterValue":"200003",
"UMask":"0xd0"
},
{
"BriefDescription":"Speculative and retired indirect branches excluding calls and returns",
"PublicDescription":"Counts speculatively miss-predicted indirect branches at execution time. Counts for indirect near CALL or JMP instructions (RET excluded).",
"BriefDescription":"Count XClk pulses when this thread is unhalted and the other thread is halted.",
"EventCode":"0x3C",
"EventName":"CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"SampleAfterValue":"100003",
"UMask":"0x2"
},
{
"BriefDescription":"Reference cycles when the core is not in halt state.",
"EventName":"CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription":"This event counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. \nNote: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. This event is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
"SampleAfterValue":"2000003",
"UMask":"0x3"
},
{
"BriefDescription":"Reference cycles when the thread is unhalted (counts at 100 MHz rate)",
"EventCode":"0x3C",
"EventName":"CPU_CLK_UNHALTED.REF_XCLK",
"PublicDescription":"Reference cycles when the thread is unhalted (counts at 100 MHz rate).",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"AnyThread":"1",
"BriefDescription":"Reference cycles when the at least one thread on the physical core is unhalted (counts at 100 MHz rate).",
"EventCode":"0x3C",
"EventName":"CPU_CLK_UNHALTED.REF_XCLK_ANY",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"Core cycles when the thread is not in halt state",
"EventName":"CPU_CLK_UNHALTED.THREAD",
"PublicDescription":"This event counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events.",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"AnyThread":"1",
"BriefDescription":"Core cycles when at least one thread on the physical core is not in halt state.",
"EventName":"CPU_CLK_UNHALTED.THREAD_ANY",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"Thread cycles when thread is not in halt state",
"EventCode":"0x3C",
"EventName":"CPU_CLK_UNHALTED.THREAD_P",
"PublicDescription":"This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
"SampleAfterValue":"2000003"
},
{
"AnyThread":"1",
"BriefDescription":"Core cycles when at least one thread on the physical core is not in halt state.",
"EventCode":"0x3C",
"EventName":"CPU_CLK_UNHALTED.THREAD_P_ANY",
"SampleAfterValue":"2000003"
},
{
"BriefDescription":"Cycles while L1 cache miss demand load is outstanding.",
"CounterMask":"8",
"EventCode":"0xA3",
"EventName":"CYCLE_ACTIVITY.CYCLES_L1D_MISS",
"SampleAfterValue":"2000003",
"UMask":"0x8"
},
{
"BriefDescription":"Cycles while L1 cache miss demand load is outstanding.",
"CounterMask":"8",
"EventCode":"0xA3",
"EventName":"CYCLE_ACTIVITY.CYCLES_L1D_PENDING",
"PublicDescription":"Counts number of cycles the CPU has at least one pending demand load request missing the L1 data cache.",
"SampleAfterValue":"2000003",
"UMask":"0x8"
},
{
"BriefDescription":"Cycles while L2 cache miss demand load is outstanding.",
"CounterMask":"1",
"EventCode":"0xA3",
"EventName":"CYCLE_ACTIVITY.CYCLES_L2_MISS",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Cycles while L2 cache miss demand load is outstanding.",
"CounterMask":"1",
"EventCode":"0xA3",
"EventName":"CYCLE_ACTIVITY.CYCLES_L2_PENDING",
"PublicDescription":"Counts number of cycles the CPU has at least one pending demand* load request missing the L2 cache.",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Cycles while memory subsystem has an outstanding load.",
"CounterMask":"2",
"EventCode":"0xA3",
"EventName":"CYCLE_ACTIVITY.CYCLES_LDM_PENDING",
"PublicDescription":"Counts number of cycles the CPU has at least one pending demand load request (that is cycles with non-completed load waiting for its data from memory subsystem).",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"Cycles while memory subsystem has an outstanding load.",
"CounterMask":"2",
"EventCode":"0xA3",
"EventName":"CYCLE_ACTIVITY.CYCLES_MEM_ANY",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"This event increments by 1 for every cycle where there was no execute for this thread.",
"CounterMask":"4",
"EventCode":"0xA3",
"EventName":"CYCLE_ACTIVITY.CYCLES_NO_EXECUTE",
"PublicDescription":"Counts number of cycles nothing is executed on any execution port.",
"SampleAfterValue":"2000003",
"UMask":"0x4"
},
{
"BriefDescription":"Execution stalls while L1 cache miss demand load is outstanding.",
"CounterMask":"12",
"EventCode":"0xA3",
"EventName":"CYCLE_ACTIVITY.STALLS_L1D_MISS",
"SampleAfterValue":"2000003",
"UMask":"0xc"
},
{
"BriefDescription":"Execution stalls while L1 cache miss demand load is outstanding.",
"CounterMask":"12",
"EventCode":"0xA3",
"EventName":"CYCLE_ACTIVITY.STALLS_L1D_PENDING",
"PublicDescription":"Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache.",
"SampleAfterValue":"2000003",
"UMask":"0xc"
},
{
"BriefDescription":"Execution stalls while L2 cache miss demand load is outstanding.",
"CounterMask":"5",
"EventCode":"0xA3",
"EventName":"CYCLE_ACTIVITY.STALLS_L2_MISS",
"SampleAfterValue":"2000003",
"UMask":"0x5"
},
{
"BriefDescription":"Execution stalls while L2 cache miss demand load is outstanding.",
"CounterMask":"5",
"EventCode":"0xA3",
"EventName":"CYCLE_ACTIVITY.STALLS_L2_PENDING",
"PublicDescription":"Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache.(as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands.",
"SampleAfterValue":"2000003",
"UMask":"0x5"
},
{
"BriefDescription":"Execution stalls while memory subsystem has an outstanding load.",
"CounterMask":"6",
"EventCode":"0xA3",
"EventName":"CYCLE_ACTIVITY.STALLS_LDM_PENDING",
"PublicDescription":"Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request.",
"SampleAfterValue":"2000003",
"UMask":"0x6"
},
{
"BriefDescription":"Execution stalls while memory subsystem has an outstanding load.",
"CounterMask":"6",
"EventCode":"0xA3",
"EventName":"CYCLE_ACTIVITY.STALLS_MEM_ANY",
"SampleAfterValue":"2000003",
"UMask":"0x6"
},
{
"BriefDescription":"Total execution stalls.",
"CounterMask":"4",
"EventCode":"0xA3",
"EventName":"CYCLE_ACTIVITY.STALLS_TOTAL",
"SampleAfterValue":"2000003",
"UMask":"0x4"
},
{
"BriefDescription":"Stalls caused by changing prefix length of the instruction.",
"PublicDescription":"This event counts stalls occurred due to changing prefix length (66, 67 or REX.W when they change the length of the decoded instruction). Occurrences counting is proportional to the number of prefixes in a 16B-line. This may result in the following penalties: three-cycle penalty for each LCP in a 16-byte chunk.",
"BriefDescription":"Instructions retired from execution.",
"EventName":"INST_RETIRED.ANY",
"PublicDescription":"This event counts the number of instructions retired from execution. For instructions that consist of multiple micro-ops, this event counts the retirement of the last micro-op of the instruction. Counting continues during hardware interrupts, traps, and inside interrupt handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. INST_RETIRED.ANY_P is counted by a programmable counter and it is an architectural performance event. \nCounting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Number of instructions retired. General Counter - architectural event",
"Errata":"BDM61",
"EventCode":"0xC0",
"EventName":"INST_RETIRED.ANY_P",
"PublicDescription":"This event counts the number of instructions (EOMs) retired. Counting covers macro-fused instructions individually (that is, increments by two).",
"SampleAfterValue":"2000003"
},
{
"BriefDescription":"Precise instruction retired event with HW to reduce effect of PEBS shadow in IP distribution",
"Errata":"BDM11, BDM55",
"EventCode":"0xC0",
"EventName":"INST_RETIRED.PREC_DIST",
"PEBS":"2",
"PublicDescription":"This is a precise version (that is, uses PEBS) of the event that counts instructions retired.",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"FP operations retired. X87 FP operations that have no exceptions:",
"EventCode":"0xC0",
"EventName":"INST_RETIRED.X87",
"PublicDescription":"This event counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling.",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"Cycles when Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the thread",
"EventCode":"0x0D",
"EventName":"INT_MISC.RAT_STALL_CYCLES",
"PublicDescription":"This event counts the number of cycles during which Resource Allocation Table (RAT) external stall is sent to Instruction Decode Queue (IDQ) for the current thread. This also includes the cycles during which the Allocator is serving another thread.",
"SampleAfterValue":"2000003",
"UMask":"0x8"
},
{
"BriefDescription":"Core cycles the allocator was stalled due to recovery from earlier clear event for this thread (e.g. misprediction or memory nuke)",
"CounterMask":"1",
"EventCode":"0x0D",
"EventName":"INT_MISC.RECOVERY_CYCLES",
"PublicDescription":"Cycles checkpoints in Resource Allocation Table (RAT) are recovering from JEClear or machine clear.",
"SampleAfterValue":"2000003",
"UMask":"0x3"
},
{
"AnyThread":"1",
"BriefDescription":"Core cycles the allocator was stalled due to recovery from earlier clear event for any thread running on the physical core (e.g. misprediction or memory nuke).",
"CounterMask":"1",
"EventCode":"0x0D",
"EventName":"INT_MISC.RECOVERY_CYCLES_ANY",
"SampleAfterValue":"2000003",
"UMask":"0x3"
},
{
"BriefDescription":"This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.",
"EventCode":"0x03",
"EventName":"LD_BLOCKS.NO_SR",
"SampleAfterValue":"100003",
"UMask":"0x8"
},
{
"BriefDescription":"Cases when loads get true Block-on-Store blocking code preventing store forwarding",
"EventCode":"0x03",
"EventName":"LD_BLOCKS.STORE_FORWARD",
"PublicDescription":"This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when:\n - preceding store conflicts with the load (incomplete overlap);\n - store forwarding is impossible due to u-arch limitations;\n - preceding lock RMW operations are not forwarded;\n - store has the no-forward bit set (uncacheable/page-split/masked stores);\n - all-blocking stores are used (mostly, fences and port I/O);\nand others.\nThe most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events.\nSee the table of not supported store forwards in the Optimization Guide.",
"SampleAfterValue":"100003",
"UMask":"0x2"
},
{
"BriefDescription":"False dependencies in MOB due to partial compare",
"EventCode":"0x07",
"EventName":"LD_BLOCKS_PARTIAL.ADDRESS_ALIAS",
"PublicDescription":"This event counts false dependencies in MOB when the partial comparison upon loose net check and dependency was resolved by the Enhanced Loose net mechanism. This may not result in high performance penalties. Loose net checks can fail when loads and stores are 4k aliased.",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"Not software-prefetch load dispatches that hit FB allocated for hardware prefetch",
"EventCode":"0x4C",
"EventName":"LOAD_HIT_PRE.HW_PF",
"PublicDescription":"This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the hardware prefetch.",
"SampleAfterValue":"100003",
"UMask":"0x2"
},
{
"BriefDescription":"Not software-prefetch load dispatches that hit FB allocated for software prefetch",
"EventCode":"0x4c",
"EventName":"LOAD_HIT_PRE.SW_PF",
"PublicDescription":"This event counts all not software-prefetch load dispatches that hit the fill buffer (FB) allocated for the software prefetch. It can also be incremented by some lock instructions. So it should only be used with profiling so that the locks can be excluded by asm inspection of the nearby instructions.",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"Cycles 4 Uops delivered by the LSD, but didn't come from the decoder.",
"CounterMask":"4",
"EventCode":"0xA8",
"EventName":"LSD.CYCLES_4_UOPS",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Cycles Uops delivered by the LSD, but didn't come from the decoder.",
"CounterMask":"1",
"EventCode":"0xA8",
"EventName":"LSD.CYCLES_ACTIVE",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Number of Uops delivered by the LSD.",
"EventCode":"0xA8",
"EventName":"LSD.UOPS",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Number of machine clears (nukes) of any type.",
"CounterMask":"1",
"EdgeDetect":"1",
"EventCode":"0xC3",
"EventName":"MACHINE_CLEARS.COUNT",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"Cycles there was a Nuke. Account for both thread-specific and All Thread Nukes.",
"EventCode":"0xC3",
"EventName":"MACHINE_CLEARS.CYCLES",
"PublicDescription":"This event counts both thread-specific (TS) and all-thread (AT) nukes.",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"This event counts the number of executed Intel AVX masked load operations that refer to an illegal address range with the mask bits set to 0.",
"EventCode":"0xC3",
"EventName":"MACHINE_CLEARS.MASKMOV",
"PublicDescription":"Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault.",
"BriefDescription":"Cycles stalled due to re-order buffer full.",
"EventCode":"0xA2",
"EventName":"RESOURCE_STALLS.ROB",
"PublicDescription":"This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.",
"SampleAfterValue":"2000003",
"UMask":"0x10"
},
{
"BriefDescription":"Cycles stalled due to no eligible RS entry available.",
"EventCode":"0xA2",
"EventName":"RESOURCE_STALLS.RS",
"PublicDescription":"This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end.",
"SampleAfterValue":"2000003",
"UMask":"0x4"
},
{
"BriefDescription":"Cycles stalled due to no store buffers available. (not including draining form sync).",
"EventCode":"0xA2",
"EventName":"RESOURCE_STALLS.SB",
"PublicDescription":"This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end.",
"SampleAfterValue":"2000003",
"UMask":"0x8"
},
{
"BriefDescription":"Count cases of saving new LBR",
"EventCode":"0xCC",
"EventName":"ROB_MISC_EVENTS.LBR_INSERTS",
"PublicDescription":"This event counts cases of saving new LBR records by hardware. This assumes proper enabling of LBRs and takes into account LBR filtering done by the LBR_SELECT register.",
"SampleAfterValue":"2000003",
"UMask":"0x20"
},
{
"BriefDescription":"Cycles when Reservation Station (RS) is empty for the thread",
"EventCode":"0x5E",
"EventName":"RS_EVENTS.EMPTY_CYCLES",
"PublicDescription":"This event counts cycles during which the reservation station (RS) is empty for the thread.\nNote: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues.",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.",
"CounterMask":"1",
"EdgeDetect":"1",
"EventCode":"0x5E",
"EventName":"RS_EVENTS.EMPTY_END",
"Invert":"1",
"SampleAfterValue":"200003",
"UMask":"0x1"
},
{
"BriefDescription":"Cycles per thread when uops are executed in port 0",
"EventCode":"0xA1",
"EventName":"UOPS_DISPATCHED_PORT.PORT_0",
"PublicDescription":"This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Cycles per thread when uops are executed in port 1",
"EventCode":"0xA1",
"EventName":"UOPS_DISPATCHED_PORT.PORT_1",
"PublicDescription":"This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"Cycles per thread when uops are executed in port 2",
"EventCode":"0xA1",
"EventName":"UOPS_DISPATCHED_PORT.PORT_2",
"PublicDescription":"This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
"SampleAfterValue":"2000003",
"UMask":"0x4"
},
{
"BriefDescription":"Cycles per thread when uops are executed in port 3",
"EventCode":"0xA1",
"EventName":"UOPS_DISPATCHED_PORT.PORT_3",
"PublicDescription":"This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
"SampleAfterValue":"2000003",
"UMask":"0x8"
},
{
"BriefDescription":"Cycles per thread when uops are executed in port 4",
"EventCode":"0xA1",
"EventName":"UOPS_DISPATCHED_PORT.PORT_4",
"PublicDescription":"This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
"SampleAfterValue":"2000003",
"UMask":"0x10"
},
{
"BriefDescription":"Cycles per thread when uops are executed in port 5",
"EventCode":"0xA1",
"EventName":"UOPS_DISPATCHED_PORT.PORT_5",
"PublicDescription":"This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
"SampleAfterValue":"2000003",
"UMask":"0x20"
},
{
"BriefDescription":"Cycles per thread when uops are executed in port 6",
"EventCode":"0xA1",
"EventName":"UOPS_DISPATCHED_PORT.PORT_6",
"PublicDescription":"This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
"SampleAfterValue":"2000003",
"UMask":"0x40"
},
{
"BriefDescription":"Cycles per thread when uops are executed in port 7",
"EventCode":"0xA1",
"EventName":"UOPS_DISPATCHED_PORT.PORT_7",
"PublicDescription":"This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
"SampleAfterValue":"2000003",
"UMask":"0x80"
},
{
"BriefDescription":"Number of uops executed on the core.",
"EventCode":"0xB1",
"EventName":"UOPS_EXECUTED.CORE",
"PublicDescription":"Number of uops executed from any thread.",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"Cycles at least 1 micro-op is executed from any thread on physical core.",
"CounterMask":"1",
"EventCode":"0xb1",
"EventName":"UOPS_EXECUTED.CORE_CYCLES_GE_1",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"Cycles at least 2 micro-op is executed from any thread on physical core.",
"CounterMask":"2",
"EventCode":"0xb1",
"EventName":"UOPS_EXECUTED.CORE_CYCLES_GE_2",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"Cycles at least 3 micro-op is executed from any thread on physical core.",
"CounterMask":"3",
"EventCode":"0xb1",
"EventName":"UOPS_EXECUTED.CORE_CYCLES_GE_3",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"Cycles at least 4 micro-op is executed from any thread on physical core.",
"CounterMask":"4",
"EventCode":"0xb1",
"EventName":"UOPS_EXECUTED.CORE_CYCLES_GE_4",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"Cycles with no micro-ops executed from any thread on physical core.",
"EventCode":"0xb1",
"EventName":"UOPS_EXECUTED.CORE_CYCLES_NONE",
"Invert":"1",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"Cycles where at least 1 uop was executed per-thread.",
"CounterMask":"1",
"EventCode":"0xB1",
"EventName":"UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Cycles where at least 2 uops were executed per-thread.",
"BriefDescription":"Counts number of cycles no uops were dispatched to be executed on this thread.",
"CounterMask":"1",
"EventCode":"0xB1",
"EventName":"UOPS_EXECUTED.STALL_CYCLES",
"Invert":"1",
"PublicDescription":"This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts the number of uops to be executed per-thread each cycle.",
"EventCode":"0xB1",
"EventName":"UOPS_EXECUTED.THREAD",
"PublicDescription":"Number of uops to be executed per-thread each cycle.",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Cycles per thread when uops are executed in port 0",
"EventCode":"0xA1",
"EventName":"UOPS_EXECUTED_PORT.PORT_0",
"PublicDescription":"This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0.",
"BriefDescription":"Cycles per thread when uops are executed in port 1",
"EventCode":"0xA1",
"EventName":"UOPS_EXECUTED_PORT.PORT_1",
"PublicDescription":"This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1.",
"BriefDescription":"Cycles per thread when uops are executed in port 2",
"EventCode":"0xA1",
"EventName":"UOPS_EXECUTED_PORT.PORT_2",
"PublicDescription":"This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2.",
"SampleAfterValue":"2000003",
"UMask":"0x4"
},
{
"AnyThread":"1",
"BriefDescription":"Cycles per core when uops are dispatched to port 2.",
"EventCode":"0xA1",
"EventName":"UOPS_EXECUTED_PORT.PORT_2_CORE",
"SampleAfterValue":"2000003",
"UMask":"0x4"
},
{
"BriefDescription":"Cycles per thread when uops are executed in port 3",
"EventCode":"0xA1",
"EventName":"UOPS_EXECUTED_PORT.PORT_3",
"PublicDescription":"This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3.",
"SampleAfterValue":"2000003",
"UMask":"0x8"
},
{
"AnyThread":"1",
"BriefDescription":"Cycles per core when uops are dispatched to port 3.",
"EventCode":"0xA1",
"EventName":"UOPS_EXECUTED_PORT.PORT_3_CORE",
"SampleAfterValue":"2000003",
"UMask":"0x8"
},
{
"BriefDescription":"Cycles per thread when uops are executed in port 4",
"EventCode":"0xA1",
"EventName":"UOPS_EXECUTED_PORT.PORT_4",
"PublicDescription":"This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4.",
"BriefDescription":"Cycles per thread when uops are executed in port 5",
"EventCode":"0xA1",
"EventName":"UOPS_EXECUTED_PORT.PORT_5",
"PublicDescription":"This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5.",
"BriefDescription":"Cycles per thread when uops are executed in port 6",
"EventCode":"0xA1",
"EventName":"UOPS_EXECUTED_PORT.PORT_6",
"PublicDescription":"This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6.",
"BriefDescription":"Cycles per thread when uops are executed in port 7",
"EventCode":"0xA1",
"EventName":"UOPS_EXECUTED_PORT.PORT_7",
"PublicDescription":"This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.",
"SampleAfterValue":"2000003",
"UMask":"0x80"
},
{
"AnyThread":"1",
"BriefDescription":"Cycles per core when uops are dispatched to port 7.",
"EventCode":"0xA1",
"EventName":"UOPS_EXECUTED_PORT.PORT_7_CORE",
"SampleAfterValue":"2000003",
"UMask":"0x80"
},
{
"BriefDescription":"Uops that Resource Allocation Table (RAT) issues to Reservation Station (RS)",
"EventCode":"0x0E",
"EventName":"UOPS_ISSUED.ANY",
"PublicDescription":"This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS).",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch.",
"EventCode":"0x0E",
"EventName":"UOPS_ISSUED.FLAGS_MERGE",
"PublicDescription":"Number of flags-merge uops being allocated. Such uops considered perf sensitive\n added by GSR u-arch.",
"SampleAfterValue":"2000003",
"UMask":"0x10"
},
{
"BriefDescription":"Number of Multiply packed/scalar single precision uops allocated.",
"EventCode":"0x0E",
"EventName":"UOPS_ISSUED.SINGLE_MUL",
"SampleAfterValue":"2000003",
"UMask":"0x40"
},
{
"BriefDescription":"Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not.",
"EventCode":"0x0E",
"EventName":"UOPS_ISSUED.SLOW_LEA",
"SampleAfterValue":"2000003",
"UMask":"0x20"
},
{
"BriefDescription":"Cycles when Resource Allocation Table (RAT) does not issue Uops to Reservation Station (RS) for the thread",
"CounterMask":"1",
"EventCode":"0x0E",
"EventName":"UOPS_ISSUED.STALL_CYCLES",
"Invert":"1",
"PublicDescription":"This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Actually retired uops.",
"EventCode":"0xC2",
"EventName":"UOPS_RETIRED.ALL",
"PEBS":"1",
"PublicDescription":"This event counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight.",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Retirement slots used.",
"EventCode":"0xC2",
"EventName":"UOPS_RETIRED.RETIRE_SLOTS",
"PEBS":"1",
"PublicDescription":"This event counts the number of retirement slots used.",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"Cycles without actually retired uops.",
"CounterMask":"1",
"EventCode":"0xC2",
"EventName":"UOPS_RETIRED.STALL_CYCLES",
"Invert":"1",
"PublicDescription":"This event counts cycles without actually retired uops.",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Cycles with less than 10 actually retired uops.",
"CounterMask":"16",
"EventCode":"0xC2",
"EventName":"UOPS_RETIRED.TOTAL_CYCLES",
"Invert":"1",
"PublicDescription":"Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.",
