"BriefDescription":"Counts the total number of branch instructions retired for all branch types.",
"EventCode":"0xc4",
"EventName":"BR_INST_RETIRED.ALL_BRANCHES",
"PEBS":"1",
"PublicDescription":"Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for.",
"SampleAfterValue":"200003"
},
{
"BriefDescription":"Counts the number of near CALL branch instructions retired.",
"EventCode":"0xc4",
"EventName":"BR_INST_RETIRED.CALL",
"PEBS":"1",
"SampleAfterValue":"200003",
"UMask":"0xf9"
},
{
"BriefDescription":"Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return.",
"EventCode":"0xc4",
"EventName":"BR_INST_RETIRED.FAR_BRANCH",
"PEBS":"1",
"SampleAfterValue":"200003",
"UMask":"0xbf"
},
{
"BriefDescription":"Counts the number of near indirect CALL branch instructions retired.",
"EventCode":"0xc4",
"EventName":"BR_INST_RETIRED.IND_CALL",
"PEBS":"1",
"SampleAfterValue":"200003",
"UMask":"0xfb"
},
{
"BriefDescription":"Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches.",
"EventCode":"0xc4",
"EventName":"BR_INST_RETIRED.JCC",
"PEBS":"1",
"SampleAfterValue":"200003",
"UMask":"0x7e"
},
{
"BriefDescription":"Counts the number of near indirect JMP and near indirect CALL branch instructions retired.",
"EventCode":"0xc4",
"EventName":"BR_INST_RETIRED.NON_RETURN_IND",
"PEBS":"1",
"SampleAfterValue":"200003",
"UMask":"0xeb"
},
{
"BriefDescription":"Counts the number of near relative CALL branch instructions retired.",
"EventCode":"0xc4",
"EventName":"BR_INST_RETIRED.REL_CALL",
"PEBS":"1",
"SampleAfterValue":"200003",
"UMask":"0xfd"
},
{
"BriefDescription":"Counts the number of near RET branch instructions retired.",
"EventCode":"0xc4",
"EventName":"BR_INST_RETIRED.RETURN",
"PEBS":"1",
"SampleAfterValue":"200003",
"UMask":"0xf7"
},
{
"BriefDescription":"Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired.",
"EventCode":"0xc4",
"EventName":"BR_INST_RETIRED.TAKEN_JCC",
"PEBS":"1",
"SampleAfterValue":"200003",
"UMask":"0xfe"
},
{
"BriefDescription":"Counts the total number of mispredicted branch instructions retired for all branch types.",
"EventCode":"0xc5",
"EventName":"BR_MISP_RETIRED.ALL_BRANCHES",
"PEBS":"1",
"PublicDescription":"Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.",
"SampleAfterValue":"200003"
},
{
"BriefDescription":"Counts the number of mispredicted near indirect CALL branch instructions retired.",
"EventCode":"0xc5",
"EventName":"BR_MISP_RETIRED.IND_CALL",
"PEBS":"1",
"SampleAfterValue":"200003",
"UMask":"0xfb"
},
{
"BriefDescription":"Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired.",
"EventCode":"0xc5",
"EventName":"BR_MISP_RETIRED.JCC",
"PEBS":"1",
"SampleAfterValue":"200003",
"UMask":"0x7e"
},
{
"BriefDescription":"Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.",
"EventCode":"0xc5",
"EventName":"BR_MISP_RETIRED.NON_RETURN_IND",
"PEBS":"1",
"SampleAfterValue":"200003",
"UMask":"0xeb"
},
{
"BriefDescription":"Counts the number of mispredicted near RET branch instructions retired.",
"EventCode":"0xc5",
"EventName":"BR_MISP_RETIRED.RETURN",
"PEBS":"1",
"SampleAfterValue":"200003",
"UMask":"0xf7"
},
{
"BriefDescription":"Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired.",
"EventCode":"0xc5",
"EventName":"BR_MISP_RETIRED.TAKEN_JCC",
"PEBS":"1",
"SampleAfterValue":"200003",
"UMask":"0xfe"
},
{
"BriefDescription":"Counts the total number of BTCLEARS.",
"EventCode":"0xe8",
"EventName":"BTCLEAR.ANY",
"PublicDescription":"Counts the total number of BTCLEARS which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
"SampleAfterValue":"200003"
},
{
"BriefDescription":"Counts the number of unhalted core clock cycles. (Fixed event)",
"EventName":"CPU_CLK_UNHALTED.CORE",
"PublicDescription":"Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"Counts the number of unhalted core clock cycles.",
"EventCode":"0x3c",
"EventName":"CPU_CLK_UNHALTED.CORE_P",
"PublicDescription":"Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.",
"SampleAfterValue":"2000003"
},
{
"BriefDescription":"Counts the number of unhalted reference clock cycles at TSC frequency.",
"EventCode":"0x3c",
"EventName":"CPU_CLK_UNHALTED.REF",
"PublicDescription":"Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)",
"EventName":"CPU_CLK_UNHALTED.REF_TSC",
"PublicDescription":"Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.",
"SampleAfterValue":"2000003",
"UMask":"0x3"
},
{
"BriefDescription":"Counts the number of unhalted reference clock cycles at TSC frequency.",
"EventCode":"0x3c",
"EventName":"CPU_CLK_UNHALTED.REF_TSC_P",
"PublicDescription":"Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.",
"BriefDescription":"Counts the number of cycles the integer divider is busy.",
"EventCode":"0xcd",
"EventName":"CYCLES_DIV_BUSY.IDIV",
"PublicDescription":"Counts the number of cycles the integer divider is busy. Does not imply a stall waiting for the divider.",
"SampleAfterValue":"200003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts the total number of instructions retired. (Fixed event)",
"EventName":"INST_RETIRED.ANY",
"PEBS":"1",
"PublicDescription":"Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0.",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts the total number of instructions retired.",
"EventCode":"0xc0",
"EventName":"INST_RETIRED.ANY_P",
"PEBS":"1",
"PublicDescription":"Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general purpose performance counter.",
"SampleAfterValue":"2000003"
},
{
"BriefDescription":"Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.",
"EventCode":"0x03",
"EventName":"LD_BLOCKS.4K_ALIAS",
"PEBS":"1",
"SampleAfterValue":"1000003",
"UMask":"0x4"
},
{
"BriefDescription":"Counts the number of retired loads that are blocked for any of the following reasons: DTLB miss, address alias, store forward or data unknown (includes memory disambiguation blocks and ESP consuming load blocks).",
"EventCode":"0x03",
"EventName":"LD_BLOCKS.ALL",
"PEBS":"1",
"SampleAfterValue":"1000003",
"UMask":"0x10"
},
{
"BriefDescription":"Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.",
"EventCode":"0x03",
"EventName":"LD_BLOCKS.DATA_UNKNOWN",
"PEBS":"1",
"SampleAfterValue":"1000003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts the number of retired loads that are blocked because its address partially overlapped with an older store.",
"EventCode":"0x03",
"EventName":"LD_BLOCKS.STORE_FORWARD",
"PEBS":"1",
"SampleAfterValue":"1000003",
"UMask":"0x2"
},
{
"BriefDescription":"Counts the total number of machine clears for any reason including, but not limited to, memory ordering, memory disambiguation, SMC, and FP assist.",
"EventCode":"0xc3",
"EventName":"MACHINE_CLEARS.ANY",
"SampleAfterValue":"20003"
},
{
"BriefDescription":"Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.",
"EventCode":"0xc3",
"EventName":"MACHINE_CLEARS.DISAMBIGUATION",
"SampleAfterValue":"20003",
"UMask":"0x8"
},
{
"BriefDescription":"Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs.",
"EventCode":"0xc3",
"EventName":"MACHINE_CLEARS.PAGE_FAULT",
"SampleAfterValue":"20003",
"UMask":"0x20"
},
{
"BriefDescription":"Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.",
"EventCode":"0xc3",
"EventName":"MACHINE_CLEARS.SMC",
"SampleAfterValue":"20003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
"EventCode":"0x73",
"EventName":"TOPDOWN_BAD_SPECULATION.ALL",
"PublicDescription":"Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
"SampleAfterValue":"1000003",
"UMask":"0x6"
},
{
"BriefDescription":"Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.",
"EventCode":"0x73",
"EventName":"TOPDOWN_BAD_SPECULATION.FASTNUKE",
"SampleAfterValue":"1000003",
"UMask":"0x2"
},
{
"BriefDescription":"Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.",
"BriefDescription":"Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.",
"EventCode":"0x74",
"EventName":"TOPDOWN_BE_BOUND.MEM_SCHEDULER",
"SampleAfterValue":"1000003",
"UMask":"0x2"
},
{
"BriefDescription":"Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.",
"EventCode":"0x74",
"EventName":"TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER",
"SampleAfterValue":"1000003",
"UMask":"0x8"
},
{
"BriefDescription":"Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).",
"EventCode":"0x74",
"EventName":"TOPDOWN_BE_BOUND.REGISTER",
"SampleAfterValue":"1000003",
"UMask":"0x20"
},
{
"BriefDescription":"Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).",
"EventCode":"0x74",
"EventName":"TOPDOWN_BE_BOUND.REORDER_BUFFER",
"SampleAfterValue":"1000003",
"UMask":"0x40"
},
{
"BriefDescription":"Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).",
"BriefDescription":"Counts the total number of issue slots every cycle that were not consumed by the backend due to frontend stalls.",
"EventCode":"0x71",
"EventName":"TOPDOWN_FE_BOUND.ALL",
"SampleAfterValue":"1000003"
},
{
"BriefDescription":"Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.",
"EventCode":"0x71",
"EventName":"TOPDOWN_FE_BOUND.BRANCH_DETECT",
"PublicDescription":"Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
"SampleAfterValue":"1000003",
"UMask":"0x2"
},
{
"BriefDescription":"Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.",
"EventCode":"0x71",
"EventName":"TOPDOWN_FE_BOUND.BRANCH_RESTEER",
"PublicDescription":"Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
"SampleAfterValue":"1000003",
"UMask":"0x40"
},
{
"BriefDescription":"Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).",
"EventCode":"0x71",
"EventName":"TOPDOWN_FE_BOUND.CISC",
"SampleAfterValue":"1000003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.",
"EventCode":"0x71",
"EventName":"TOPDOWN_FE_BOUND.DECODE",
"SampleAfterValue":"1000003",
"UMask":"0x8"
},
{
"BriefDescription":"Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.",
"EventCode":"0x71",
"EventName":"TOPDOWN_FE_BOUND.ITLB",
"PublicDescription":"Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.",
"SampleAfterValue":"1000003",
"UMask":"0x10"
},
{
"BriefDescription":"Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.",
"EventCode":"0x71",
"EventName":"TOPDOWN_FE_BOUND.OTHER",
"SampleAfterValue":"1000003",
"UMask":"0x80"
},
{
"BriefDescription":"Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.",
"EventCode":"0x71",
"EventName":"TOPDOWN_FE_BOUND.PREDECODE",
"SampleAfterValue":"1000003",
"UMask":"0x4"
},
{
"BriefDescription":"Counts the total number of consumed retirement slots.",
"EventCode":"0xc2",
"EventName":"TOPDOWN_RETIRING.ALL",
"PEBS":"1",
"SampleAfterValue":"1000003"
},
{
"BriefDescription":"Counts the number of uops issued by the front end every cycle.",
"EventCode":"0x0e",
"EventName":"UOPS_ISSUED.ANY",
"PublicDescription":"Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued.",
"SampleAfterValue":"200003"
},
{
"BriefDescription":"Counts the total number of uops retired.",
"EventCode":"0xc2",
"EventName":"UOPS_RETIRED.ALL",
"PEBS":"1",
"SampleAfterValue":"2000003"
},
{
"BriefDescription":"Counts the number of integer divide uops retired.",
"EventCode":"0xc2",
"EventName":"UOPS_RETIRED.IDIV",
"PEBS":"1",
"SampleAfterValue":"2000003",
"UMask":"0x10"
},
{
"BriefDescription":"Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).",
"EventCode":"0xc2",
"EventName":"UOPS_RETIRED.MS",
"PEBS":"1",
"PublicDescription":"Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Counts the number of x87 uops retired, includes those in MS flows.",
