"BriefDescription":"Allocated L1D data cache lines in M state.",
"EventCode":"0x51",
"EventName":"L1D.ALLOCATED_IN_M",
"SampleAfterValue":"2000003",
"UMask":"0x2"
},
{
"BriefDescription":"Cache lines in M state evicted out of L1D due to Snoop HitM or dirty line replacement.",
"EventCode":"0x51",
"EventName":"L1D.ALL_M_REPLACEMENT",
"SampleAfterValue":"2000003",
"UMask":"0x8"
},
{
"BriefDescription":"L1D data cache lines in M state evicted due to replacement.",
"EventCode":"0x51",
"EventName":"L1D.EVICTION",
"SampleAfterValue":"2000003",
"UMask":"0x4"
},
{
"BriefDescription":"L1D data line replacements.",
"EventCode":"0x51",
"EventName":"L1D.REPLACEMENT",
"PublicDescription":"This event counts L1D data line replacements. Replacements occur when a new line is brought into the cache, causing eviction of a line loaded earlier.",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Cycles when dispatched loads are cancelled due to L1D bank conflicts with other load ports.",
"BriefDescription":"Cycles with L1D load Misses outstanding.",
"CounterMask":"1",
"EventCode":"0x48",
"EventName":"L1D_PEND_MISS.PENDING_CYCLES",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"AnyThread":"1",
"BriefDescription":"Cycles with L1D load Misses outstanding from any thread on physical core.",
"CounterMask":"1",
"EventCode":"0x48",
"EventName":"L1D_PEND_MISS.PENDING_CYCLES_ANY",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Not rejected writebacks from L1D to L2 cache lines in any state.",
"EventCode":"0x28",
"EventName":"L2_L1D_WB_RQSTS.ALL",
"SampleAfterValue":"200003",
"UMask":"0xf"
},
{
"BriefDescription":"Not rejected writebacks from L1D to L2 cache lines in E state.",
"EventCode":"0x28",
"EventName":"L2_L1D_WB_RQSTS.HIT_E",
"SampleAfterValue":"200003",
"UMask":"0x4"
},
{
"BriefDescription":"Not rejected writebacks from L1D to L2 cache lines in M state.",
"EventCode":"0x28",
"EventName":"L2_L1D_WB_RQSTS.HIT_M",
"SampleAfterValue":"200003",
"UMask":"0x8"
},
{
"BriefDescription":"Not rejected writebacks from L1D to L2 cache lines in S state.",
"EventCode":"0x28",
"EventName":"L2_L1D_WB_RQSTS.HIT_S",
"SampleAfterValue":"200003",
"UMask":"0x2"
},
{
"BriefDescription":"Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.).",
"EventCode":"0x28",
"EventName":"L2_L1D_WB_RQSTS.MISS",
"SampleAfterValue":"200003",
"UMask":"0x1"
},
{
"BriefDescription":"L2 cache lines filling L2.",
"EventCode":"0xF1",
"EventName":"L2_LINES_IN.ALL",
"PublicDescription":"This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.",
"SampleAfterValue":"100003",
"UMask":"0x7"
},
{
"BriefDescription":"L2 cache lines in E state filling L2.",
"EventCode":"0xF1",
"EventName":"L2_LINES_IN.E",
"SampleAfterValue":"100003",
"UMask":"0x4"
},
{
"BriefDescription":"L2 cache lines in I state filling L2.",
"EventCode":"0xF1",
"EventName":"L2_LINES_IN.I",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"L2 cache lines in S state filling L2.",
"EventCode":"0xF1",
"EventName":"L2_LINES_IN.S",
"SampleAfterValue":"100003",
"UMask":"0x2"
},
{
"BriefDescription":"Clean L2 cache lines evicted by demand.",
"EventCode":"0xF2",
"EventName":"L2_LINES_OUT.DEMAND_CLEAN",
"SampleAfterValue":"100003",
"UMask":"0x1"
},
{
"BriefDescription":"Dirty L2 cache lines evicted by demand.",
"EventCode":"0xF2",
"EventName":"L2_LINES_OUT.DEMAND_DIRTY",
"SampleAfterValue":"100003",
"UMask":"0x2"
},
{
"BriefDescription":"Dirty L2 cache lines filling the L2.",
"EventCode":"0xF2",
"EventName":"L2_LINES_OUT.DIRTY_ALL",
"SampleAfterValue":"100003",
"UMask":"0xa"
},
{
"BriefDescription":"Clean L2 cache lines evicted by L2 prefetch.",
"EventCode":"0xF2",
"EventName":"L2_LINES_OUT.PF_CLEAN",
"SampleAfterValue":"100003",
"UMask":"0x4"
},
{
"BriefDescription":"Dirty L2 cache lines evicted by L2 prefetch.",
"EventCode":"0xF2",
"EventName":"L2_LINES_OUT.PF_DIRTY",
"SampleAfterValue":"100003",
"UMask":"0x8"
},
{
"BriefDescription":"L2 code requests.",
"EventCode":"0x24",
"EventName":"L2_RQSTS.ALL_CODE_RD",
"SampleAfterValue":"200003",
"UMask":"0x30"
},
{
"BriefDescription":"Demand Data Read requests.",
"EventCode":"0x24",
"EventName":"L2_RQSTS.ALL_DEMAND_DATA_RD",
"SampleAfterValue":"200003",
"UMask":"0x3"
},
{
"BriefDescription":"Requests from L2 hardware prefetchers.",
"EventCode":"0x24",
"EventName":"L2_RQSTS.ALL_PF",
"SampleAfterValue":"200003",
"UMask":"0xc0"
},
{
"BriefDescription":"RFO requests to L2 cache.",
"EventCode":"0x24",
"EventName":"L2_RQSTS.ALL_RFO",
"SampleAfterValue":"200003",
"UMask":"0xc"
},
{
"BriefDescription":"L2 cache hits when fetching instructions, code reads.",
"EventCode":"0x24",
"EventName":"L2_RQSTS.CODE_RD_HIT",
"SampleAfterValue":"200003",
"UMask":"0x10"
},
{
"BriefDescription":"L2 cache misses when fetching instructions.",
"EventCode":"0x24",
"EventName":"L2_RQSTS.CODE_RD_MISS",
"SampleAfterValue":"200003",
"UMask":"0x20"
},
{
"BriefDescription":"Demand Data Read requests that hit L2 cache.",
"EventCode":"0x24",
"EventName":"L2_RQSTS.DEMAND_DATA_RD_HIT",
"SampleAfterValue":"200003",
"UMask":"0x1"
},
{
"BriefDescription":"Requests from the L2 hardware prefetchers that hit L2 cache.",
"EventCode":"0x24",
"EventName":"L2_RQSTS.PF_HIT",
"SampleAfterValue":"200003",
"UMask":"0x40"
},
{
"BriefDescription":"Requests from the L2 hardware prefetchers that miss L2 cache.",
"EventCode":"0x24",
"EventName":"L2_RQSTS.PF_MISS",
"SampleAfterValue":"200003",
"UMask":"0x80"
},
{
"BriefDescription":"RFO requests that hit L2 cache.",
"EventCode":"0x24",
"EventName":"L2_RQSTS.RFO_HIT",
"SampleAfterValue":"200003",
"UMask":"0x4"
},
{
"BriefDescription":"RFO requests that miss L2 cache.",
"EventCode":"0x24",
"EventName":"L2_RQSTS.RFO_MISS",
"SampleAfterValue":"200003",
"UMask":"0x8"
},
{
"BriefDescription":"RFOs that access cache lines in any state.",
"EventCode":"0x27",
"EventName":"L2_STORE_LOCK_RQSTS.ALL",
"SampleAfterValue":"200003",
"UMask":"0xf"
},
{
"BriefDescription":"RFOs that hit cache lines in E state.",
"EventCode":"0x27",
"EventName":"L2_STORE_LOCK_RQSTS.HIT_E",
"SampleAfterValue":"200003",
"UMask":"0x4"
},
{
"BriefDescription":"RFOs that hit cache lines in M state.",
"EventCode":"0x27",
"EventName":"L2_STORE_LOCK_RQSTS.HIT_M",
"SampleAfterValue":"200003",
"UMask":"0x8"
},
{
"BriefDescription":"RFOs that miss cache lines.",
"EventCode":"0x27",
"EventName":"L2_STORE_LOCK_RQSTS.MISS",
"SampleAfterValue":"200003",
"UMask":"0x1"
},
{
"BriefDescription":"L2 or LLC HW prefetches that access L2 cache.",
"PublicDescription":"This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a non-modified state.",
"SampleAfterValue":"20011",
"UMask":"0x2"
},
{
"BriefDescription":"Retired load uops which data sources were HitM responses from shared LLC.",
"PublicDescription":"This event counts retired load uops that hit in the last-level cache (L3) and were found in a non-modified state in a neighboring core's private cache (same package). Since the last level cache is inclusive, hits to the L3 may require snooping the private L2 caches of any cores on the same socket that have the line. In this case, a snoop was required, and another L2 had the line in a modified state, so the line had to be invalidated in that L2 cache and transferred to the requesting L2.",
"SampleAfterValue":"20011",
"UMask":"0x4"
},
{
"BriefDescription":"Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.",
"BriefDescription":"Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
"EventCode":"0xD1",
"EventName":"MEM_LOAD_UOPS_RETIRED.HIT_LFB",
"PEBS":"1",
"SampleAfterValue":"100003",
"UMask":"0x40"
},
{
"BriefDescription":"Retired load uops with L1 cache hits as data sources.",
"EventCode":"0xD1",
"EventName":"MEM_LOAD_UOPS_RETIRED.L1_HIT",
"PEBS":"1",
"SampleAfterValue":"2000003",
"UMask":"0x1"
},
{
"BriefDescription":"Retired load uops with L2 cache hits as data sources.",
"EventCode":"0xD1",
"EventName":"MEM_LOAD_UOPS_RETIRED.L2_HIT",
"PEBS":"1",
"SampleAfterValue":"100003",
"UMask":"0x2"
},
{
"BriefDescription":"Retired load uops which data sources were data hits in LLC without snoops required.",
"EventCode":"0xD1",
"EventName":"MEM_LOAD_UOPS_RETIRED.LLC_HIT",
"PublicDescription":"This event counts retired load uops that hit in the last-level (L3) cache without snoops required.",
"SampleAfterValue":"50021",
"UMask":"0x4"
},
{
"BriefDescription":"Miss in last-level (L3) cache. Excludes Unknown data-source.",
"EventCode":"0xD1",
"EventName":"MEM_LOAD_UOPS_RETIRED.LLC_MISS",
"SampleAfterValue":"100007",
"UMask":"0x20"
},
{
"BriefDescription":"All retired load uops.",
"EventCode":"0xD0",
"EventName":"MEM_UOPS_RETIRED.ALL_LOADS",
"PEBS":"1",
"PublicDescription":"This event counts the number of load uops retired",
"SampleAfterValue":"2000003",
"UMask":"0x81"
},
{
"BriefDescription":"All retired store uops.",
"EventCode":"0xD0",
"EventName":"MEM_UOPS_RETIRED.ALL_STORES",
"PEBS":"1",
"PublicDescription":"This event counts the number of store uops retired.",
"SampleAfterValue":"2000003",
"UMask":"0x82"
},
{
"BriefDescription":"Retired load uops with locked access.",
"EventCode":"0xD0",
"EventName":"MEM_UOPS_RETIRED.LOCK_LOADS",
"PEBS":"1",
"SampleAfterValue":"100007",
"UMask":"0x21"
},
{
"BriefDescription":"Retired load uops that split across a cacheline boundary.",
"EventCode":"0xD0",
"EventName":"MEM_UOPS_RETIRED.SPLIT_LOADS",
"PEBS":"1",
"PublicDescription":"This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
"SampleAfterValue":"100003",
"UMask":"0x41"
},
{
"BriefDescription":"Retired store uops that split across a cacheline boundary.",
"EventCode":"0xD0",
"EventName":"MEM_UOPS_RETIRED.SPLIT_STORES",
"PEBS":"1",
"PublicDescription":"This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
"SampleAfterValue":"100003",
"UMask":"0x42"
},
{
"BriefDescription":"Retired load uops that miss the STLB.",
"EventCode":"0xD0",
"EventName":"MEM_UOPS_RETIRED.STLB_MISS_LOADS",
"PEBS":"1",
"SampleAfterValue":"100003",
"UMask":"0x11"
},
{
"BriefDescription":"Retired store uops that miss the STLB.",
"EventCode":"0xD0",
"EventName":"MEM_UOPS_RETIRED.STLB_MISS_STORES",
"PEBS":"1",
"SampleAfterValue":"100003",
"UMask":"0x12"
},
{
"BriefDescription":"Demand and prefetch data reads.",
"BriefDescription":"Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
"BriefDescription":"Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
"BriefDescription":"Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
"BriefDescription":"Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
"BriefDescription":"Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
"BriefDescription":"Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
"BriefDescription":"Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
"BriefDescription":"Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
"BriefDescription":"Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
"BriefDescription":"Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
"BriefDescription":"Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
"BriefDescription":"Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
"BriefDescription":"Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
"BriefDescription":"Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
"BriefDescription":"Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
"BriefDescription":"Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
"BriefDescription":"Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
"BriefDescription":"Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
"BriefDescription":"Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
"BriefDescription":"Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
"BriefDescription":"Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address",
