144 lines
12 KiB
JSON
144 lines
12 KiB
JSON
|
[
|
||
|
|
{
|
||
|
|
"BriefDescription": "This event counts the cycles the floating point divider is busy.",
|
||
|
|
"CounterMask": "1",
|
||
|
|
"EventCode": "0xb0",
|
||
|
|
"EventName": "ARITH.FPDIV_ACTIVE",
|
||
|
|
"SampleAfterValue": "1000003",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"Unit": "cpu_core"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts all microcode FP assists.",
|
||
|
|
"EventCode": "0xc1",
|
||
|
|
"EventName": "ASSISTS.FP",
|
||
|
|
"PublicDescription": "Counts all microcode Floating Point assists.",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x2",
|
||
|
|
"Unit": "cpu_core"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "ASSISTS.SSE_AVX_MIX",
|
||
|
|
"EventCode": "0xc1",
|
||
|
|
"EventName": "ASSISTS.SSE_AVX_MIX",
|
||
|
|
"SampleAfterValue": "1000003",
|
||
|
|
"UMask": "0x10",
|
||
|
|
"Unit": "cpu_core"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "FP_ARITH_DISPATCHED.PORT_0",
|
||
|
|
"EventCode": "0xb3",
|
||
|
|
"EventName": "FP_ARITH_DISPATCHED.PORT_0",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"Unit": "cpu_core"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "FP_ARITH_DISPATCHED.PORT_1",
|
||
|
|
"EventCode": "0xb3",
|
||
|
|
"EventName": "FP_ARITH_DISPATCHED.PORT_1",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x2",
|
||
|
|
"Unit": "cpu_core"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
|
||
|
|
"EventCode": "0xc7",
|
||
|
|
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
|
||
|
|
"PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x4",
|
||
|
|
"Unit": "cpu_core"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
|
||
|
|
"EventCode": "0xc7",
|
||
|
|
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
|
||
|
|
"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x8",
|
||
|
|
"Unit": "cpu_core"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
|
||
|
|
"EventCode": "0xc7",
|
||
|
|
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
|
||
|
|
"PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x10",
|
||
|
|
"Unit": "cpu_core"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
|
||
|
|
"EventCode": "0xc7",
|
||
|
|
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
|
||
|
|
"PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x20",
|
||
|
|
"Unit": "cpu_core"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single and 256-bit packed double precision FP instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, 1 for each element. Applies to SSE* and AVX* packed single precision and packed double precision FP instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per element.",
|
||
|
|
"EventCode": "0xc7",
|
||
|
|
"EventName": "FP_ARITH_INST_RETIRED.4_FLOPS",
|
||
|
|
"PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision and 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 or/and 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point and packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x18",
|
||
|
|
"Unit": "cpu_core"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired; some instructions will count twice as noted below. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
|
||
|
|
"EventCode": "0xc7",
|
||
|
|
"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
|
||
|
|
"PublicDescription": "Number of SSE/AVX computational scalar single precision and double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
|
||
|
|
"SampleAfterValue": "1000003",
|
||
|
|
"UMask": "0x3",
|
||
|
|
"Unit": "cpu_core"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
|
||
|
|
"EventCode": "0xc7",
|
||
|
|
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
|
||
|
|
"PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x1",
|
||
|
|
"Unit": "cpu_core"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
|
||
|
|
"EventCode": "0xc7",
|
||
|
|
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
|
||
|
|
"PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
|
||
|
|
"SampleAfterValue": "100003",
|
||
|
|
"UMask": "0x2",
|
||
|
|
"Unit": "cpu_core"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Number of any Vector retired FP arithmetic instructions",
|
||
|
|
"EventCode": "0xc7",
|
||
|
|
"EventName": "FP_ARITH_INST_RETIRED.VECTOR",
|
||
|
|
"PublicDescription": "Number of any Vector retired FP arithmetic instructions. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",
|
||
|
|
"SampleAfterValue": "1000003",
|
||
|
|
"UMask": "0xfc",
|
||
|
|
"Unit": "cpu_core"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",
|
||
|
|
"EventCode": "0xc3",
|
||
|
|
"EventName": "MACHINE_CLEARS.FP_ASSIST",
|
||
|
|
"PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",
|
||
|
|
"SampleAfterValue": "20003",
|
||
|
|
"UMask": "0x4",
|
||
|
|
"Unit": "cpu_atom"
|
||
|
|
},
|
||
|
|
{
|
||
|
|
"BriefDescription": "Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt).",
|
||
|
|
"EventCode": "0xc2",
|
||
|
|
"EventName": "UOPS_RETIRED.FPDIV",
|
||
|
|
"PEBS": "1",
|
||
|
|
"SampleAfterValue": "2000003",
|
||
|
|
"UMask": "0x8",
|
||
|
|
"Unit": "cpu_atom"
|
||
|
|
}
|
||
|
|
]
|