"BriefDescription":"Cycles when divide unit is busy executing divide or square root operations.",
"CounterMask":"1",
"EventCode":"0xb0",
"EventName":"ARITH.DIV_ACTIVE",
"PublicDescription":"Counts cycles when divide unit is busy executing divide or square root operations. Accounts for integer and floating-point operations.",
"SampleAfterValue":"1000003",
"UMask":"0x9",
"Unit":"cpu_core"
},
{
"BriefDescription":"This event counts the cycles the integer divider is busy.",
"CounterMask":"1",
"EventCode":"0xb0",
"EventName":"ARITH.IDIV_ACTIVE",
"SampleAfterValue":"1000003",
"UMask":"0x8",
"Unit":"cpu_core"
},
{
"BriefDescription":"Number of occurrences where a microcode assist is invoked by hardware.",
"EventCode":"0xc1",
"EventName":"ASSISTS.ANY",
"PublicDescription":"Counts the number of occurrences where a microcode assist is invoked by hardware. Examples include AD (page Access Dirty), FP and AVX related assists.",
"PublicDescription":"Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for.",
"PublicDescription":"Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.",
"PublicDescription":"Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch. When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path.",
"SampleAfterValue":"400009",
"Unit":"cpu_core"
},
{
"BriefDescription":"All mispredicted branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
"EventCode":"0xc5",
"EventName":"BR_MISP_RETIRED.ALL_BRANCHES_COST",
"PEBS":"1",
"SampleAfterValue":"400009",
"UMask":"0x44",
"Unit":"cpu_core"
},
{
"BriefDescription":"Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired.",
"BriefDescription":"Mispredicted conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
"PublicDescription":"Counts the number of conditional branch instructions retired that were mispredicted and the branch direction was not taken.",
"SampleAfterValue":"400009",
"UMask":"0x10",
"Unit":"cpu_core"
},
{
"BriefDescription":"Mispredicted non-taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
"EventCode":"0xc5",
"EventName":"BR_MISP_RETIRED.COND_NTAKEN_COST",
"PEBS":"1",
"SampleAfterValue":"400009",
"UMask":"0x50",
"Unit":"cpu_core"
},
{
"BriefDescription":"number of branch instructions retired that were mispredicted and taken.",
"EventCode":"0xc5",
"EventName":"BR_MISP_RETIRED.COND_TAKEN",
"PEBS":"1",
"PublicDescription":"Counts taken conditional mispredicted branch instructions retired.",
"SampleAfterValue":"400009",
"UMask":"0x1",
"Unit":"cpu_core"
},
{
"BriefDescription":"Mispredicted taken conditional branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
"EventCode":"0xc5",
"EventName":"BR_MISP_RETIRED.COND_TAKEN_COST",
"PEBS":"1",
"SampleAfterValue":"400009",
"UMask":"0x41",
"Unit":"cpu_core"
},
{
"BriefDescription":"Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.",
"EventCode":"0xc5",
"EventName":"BR_MISP_RETIRED.INDIRECT",
"PEBS":"1",
"SampleAfterValue":"200003",
"UMask":"0xeb",
"Unit":"cpu_atom"
},
{
"BriefDescription":"Miss-predicted near indirect branch instructions retired (excluding returns)",
"EventCode":"0xc5",
"EventName":"BR_MISP_RETIRED.INDIRECT",
"PEBS":"1",
"PublicDescription":"Counts miss-predicted near indirect branch instructions retired excluding returns. TSX abort is an indirect branch.",
"SampleAfterValue":"100003",
"UMask":"0x80",
"Unit":"cpu_core"
},
{
"BriefDescription":"Counts the number of mispredicted near indirect CALL branch instructions retired.",
"PublicDescription":"Counts retired mispredicted indirect (near taken) CALL instructions, including both register and memory indirect.",
"SampleAfterValue":"400009",
"UMask":"0x2",
"Unit":"cpu_core"
},
{
"BriefDescription":"Mispredicted indirect CALL retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
"EventCode":"0xc5",
"EventName":"BR_MISP_RETIRED.INDIRECT_CALL_COST",
"PEBS":"1",
"SampleAfterValue":"400009",
"UMask":"0x42",
"Unit":"cpu_core"
},
{
"BriefDescription":"Mispredicted near indirect branch instructions retired (excluding returns). This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
"EventCode":"0xc5",
"EventName":"BR_MISP_RETIRED.INDIRECT_COST",
"PEBS":"1",
"SampleAfterValue":"100003",
"UMask":"0xc0",
"Unit":"cpu_core"
},
{
"BriefDescription":"Number of near branch instructions retired that were mispredicted and taken.",
"EventCode":"0xc5",
"EventName":"BR_MISP_RETIRED.NEAR_TAKEN",
"PEBS":"1",
"PublicDescription":"Counts number of near branch instructions retired that were mispredicted and taken.",
"SampleAfterValue":"400009",
"UMask":"0x20",
"Unit":"cpu_core"
},
{
"BriefDescription":"Mispredicted taken near branch instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
"BriefDescription":"Counts the number of mispredicted near RET branch instructions retired.",
"EventCode":"0xc5",
"EventName":"BR_MISP_RETIRED.RETURN",
"PEBS":"1",
"SampleAfterValue":"200003",
"UMask":"0xf7",
"Unit":"cpu_atom"
},
{
"BriefDescription":"Mispredicted ret instructions retired. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch.",
"BriefDescription":"Cycle counts are evenly distributed between active threads in the Core.",
"EventCode":"0xec",
"EventName":"CPU_CLK_UNHALTED.DISTRIBUTED",
"PublicDescription":"This event distributes cycle counts between active hyperthreads, i.e., those in C0. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If all other hyperthreads are inactive (or disabled or do not exist), all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
"SampleAfterValue":"2000003",
"UMask":"0x2",
"Unit":"cpu_core"
},
{
"BriefDescription":"Core crystal clock cycles when this thread is unhalted and the other thread is halted.",
"EventCode":"0x3c",
"EventName":"CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE",
"PublicDescription":"Counts Core crystal clock cycles when current thread is unhalted and the other thread is halted.",
"SampleAfterValue":"25003",
"UMask":"0x2",
"Unit":"cpu_core"
},
{
"BriefDescription":"Core crystal clock cycles. Cycle counts are evenly distributed between active threads in the Core.",
"EventCode":"0x3c",
"EventName":"CPU_CLK_UNHALTED.REF_DISTRIBUTED",
"PublicDescription":"This event distributes Core crystal clock cycle counts between active hyperthreads, i.e., those in C0 sleep-state. A hyperthread becomes inactive when it executes the HLT or MWAIT instructions. If one thread is active in a core, all counts are attributed to this hyperthread. To obtain the full count when the Core is active, sum the counts from each hyperthread.",
"PublicDescription":"Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
"BriefDescription":"Counts the number of unhalted reference clock cycles at TSC frequency.",
"EventCode":"0x3c",
"EventName":"CPU_CLK_UNHALTED.REF_TSC_P",
"PublicDescription":"Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.",
"PublicDescription":"Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. It is counted on a dedicated fixed counter, leaving the four (eight when Hyperthreading is disabled) programmable counters available for other events. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'. The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'. After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
"PublicDescription":"Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the eight programmable counters available for other events.",
"PublicDescription":"This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time.",
"BriefDescription":"Cycles total of 3 uops are executed on all ports and Reservation Station was not empty.",
"EventCode":"0xa6",
"EventName":"EXE_ACTIVITY.3_PORTS_UTIL",
"PublicDescription":"Cycles total of 3 uops are executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue":"2000003",
"UMask":"0x8",
"Unit":"cpu_core"
},
{
"BriefDescription":"Cycles total of 4 uops are executed on all ports and Reservation Station was not empty.",
"EventCode":"0xa6",
"EventName":"EXE_ACTIVITY.4_PORTS_UTIL",
"PublicDescription":"Cycles total of 4 uops are executed on all ports and Reservation Station (RS) was not empty.",
"SampleAfterValue":"2000003",
"UMask":"0x10",
"Unit":"cpu_core"
},
{
"BriefDescription":"Execution stalls while memory subsystem has an outstanding load.",
"CounterMask":"5",
"EventCode":"0xa6",
"EventName":"EXE_ACTIVITY.BOUND_ON_LOADS",
"SampleAfterValue":"2000003",
"UMask":"0x21",
"Unit":"cpu_core"
},
{
"BriefDescription":"Cycles where the Store Buffer was full and no loads caused an execution stall.",
"CounterMask":"2",
"EventCode":"0xa6",
"EventName":"EXE_ACTIVITY.BOUND_ON_STORES",
"PublicDescription":"Counts cycles where the Store Buffer was full and no loads caused an execution stall.",
"SampleAfterValue":"1000003",
"UMask":"0x40",
"Unit":"cpu_core"
},
{
"BriefDescription":"Cycles no uop executed while RS was not empty, the SB was not full and there was no outstanding load.",
"EventCode":"0xa6",
"EventName":"EXE_ACTIVITY.EXE_BOUND_0_PORTS",
"PublicDescription":"Number of cycles total of 0 uops executed on all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) was not full and there was no outstanding load.",
"SampleAfterValue":"1000003",
"UMask":"0x80",
"Unit":"cpu_core"
},
{
"BriefDescription":"Instruction decoders utilized in a cycle",
"EventCode":"0x75",
"EventName":"INST_DECODED.DECODERS",
"PublicDescription":"Number of decoders utilized in a cycle when the MITE (legacy decode pipeline) fetches instructions.",
"SampleAfterValue":"2000003",
"UMask":"0x1",
"Unit":"cpu_core"
},
{
"BriefDescription":"Fixed Counter: Counts the number of instructions retired",
"EventName":"INST_RETIRED.ANY",
"PEBS":"1",
"SampleAfterValue":"2000003",
"UMask":"0x1",
"Unit":"cpu_atom"
},
{
"BriefDescription":"Number of instructions retired. Fixed Counter - architectural event",
"EventName":"INST_RETIRED.ANY",
"PEBS":"1",
"PublicDescription":"Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
"SampleAfterValue":"2000003",
"UMask":"0x1",
"Unit":"cpu_core"
},
{
"BriefDescription":"Counts the number of instructions retired",
"EventCode":"0xc0",
"EventName":"INST_RETIRED.ANY_P",
"PEBS":"1",
"SampleAfterValue":"2000003",
"Unit":"cpu_atom"
},
{
"BriefDescription":"Number of instructions retired. General Counter - architectural event",
"EventCode":"0xc0",
"EventName":"INST_RETIRED.ANY_P",
"PEBS":"1",
"PublicDescription":"Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter.",
"SampleAfterValue":"2000003",
"Unit":"cpu_core"
},
{
"BriefDescription":"INST_RETIRED.MACRO_FUSED",
"EventCode":"0xc0",
"EventName":"INST_RETIRED.MACRO_FUSED",
"SampleAfterValue":"2000003",
"UMask":"0x10",
"Unit":"cpu_core"
},
{
"BriefDescription":"Precise instruction retired with PEBS precise-distribution",
"EventName":"INST_RETIRED.PREC_DIST",
"PEBS":"1",
"PublicDescription":"A version of INST_RETIRED that allows for a precise distribution of samples across instructions retired. It utilizes the Precise Distribution of Instructions Retired (PDIR++) feature to fix bias in how retired instructions get sampled. Use on Fixed Counter 0.",
"SampleAfterValue":"2000003",
"UMask":"0x1",
"Unit":"cpu_core"
},
{
"BriefDescription":"Cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.",
"CounterMask":"1",
"EventCode":"0xad",
"EventName":"INT_MISC.ALL_RECOVERY_CYCLES",
"PublicDescription":"Counts cycles the Backend cluster is recovering after a miss-speculation or a Store Buffer or Load Buffer drain stall.",
"SampleAfterValue":"2000003",
"UMask":"0x3",
"Unit":"cpu_core"
},
{
"BriefDescription":"Counts cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
"EventCode":"0xad",
"EventName":"INT_MISC.CLEAR_RESTEER_CYCLES",
"PublicDescription":"Cycles after recovery from a branch misprediction or machine clear till the first uop is issued from the resteered path.",
"SampleAfterValue":"500009",
"UMask":"0x80",
"Unit":"cpu_core"
},
{
"BriefDescription":"Core cycles the allocator was stalled due to recovery from earlier clear event for this thread",
"EventCode":"0xad",
"EventName":"INT_MISC.RECOVERY_CYCLES",
"PublicDescription":"Counts core cycles when the Resource allocator was stalled due to recovery from an earlier branch misprediction or machine clear event.",
"BriefDescription":"TMA slots where uops got dropped",
"EventCode":"0xad",
"EventName":"INT_MISC.UOP_DROPPING",
"PublicDescription":"Estimated number of Top-down Microarchitecture Analysis slots that got dropped due to non front-end reasons",
"SampleAfterValue":"1000003",
"UMask":"0x10",
"Unit":"cpu_core"
},
{
"BriefDescription":"INT_VEC_RETIRED.128BIT",
"EventCode":"0xe7",
"EventName":"INT_VEC_RETIRED.128BIT",
"SampleAfterValue":"1000003",
"UMask":"0x13",
"Unit":"cpu_core"
},
{
"BriefDescription":"INT_VEC_RETIRED.256BIT",
"EventCode":"0xe7",
"EventName":"INT_VEC_RETIRED.256BIT",
"SampleAfterValue":"1000003",
"UMask":"0xac",
"Unit":"cpu_core"
},
{
"BriefDescription":"integer ADD, SUB, SAD 128-bit vector instructions.",
"EventCode":"0xe7",
"EventName":"INT_VEC_RETIRED.ADD_128",
"PublicDescription":"Number of retired integer ADD/SUB (regular or horizontal), SAD 128-bit vector instructions.",
"SampleAfterValue":"1000003",
"UMask":"0x3",
"Unit":"cpu_core"
},
{
"BriefDescription":"integer ADD, SUB, SAD 256-bit vector instructions.",
"EventCode":"0xe7",
"EventName":"INT_VEC_RETIRED.ADD_256",
"PublicDescription":"Number of retired integer ADD/SUB (regular or horizontal), SAD 256-bit vector instructions.",
"SampleAfterValue":"1000003",
"UMask":"0xc",
"Unit":"cpu_core"
},
{
"BriefDescription":"INT_VEC_RETIRED.MUL_256",
"EventCode":"0xe7",
"EventName":"INT_VEC_RETIRED.MUL_256",
"SampleAfterValue":"1000003",
"UMask":"0x80",
"Unit":"cpu_core"
},
{
"BriefDescription":"INT_VEC_RETIRED.SHUFFLES",
"EventCode":"0xe7",
"EventName":"INT_VEC_RETIRED.SHUFFLES",
"SampleAfterValue":"1000003",
"UMask":"0x40",
"Unit":"cpu_core"
},
{
"BriefDescription":"INT_VEC_RETIRED.VNNI_128",
"EventCode":"0xe7",
"EventName":"INT_VEC_RETIRED.VNNI_128",
"SampleAfterValue":"1000003",
"UMask":"0x10",
"Unit":"cpu_core"
},
{
"BriefDescription":"INT_VEC_RETIRED.VNNI_256",
"EventCode":"0xe7",
"EventName":"INT_VEC_RETIRED.VNNI_256",
"SampleAfterValue":"1000003",
"UMask":"0x20",
"Unit":"cpu_core"
},
{
"BriefDescription":"Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.",
"EventCode":"0x03",
"EventName":"LD_BLOCKS.ADDRESS_ALIAS",
"PEBS":"1",
"SampleAfterValue":"1000003",
"UMask":"0x4",
"Unit":"cpu_atom"
},
{
"BriefDescription":"Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.",
"EventCode":"0x03",
"EventName":"LD_BLOCKS.DATA_UNKNOWN",
"PEBS":"1",
"SampleAfterValue":"1000003",
"UMask":"0x1",
"Unit":"cpu_atom"
},
{
"BriefDescription":"Counts the number of retired loads that are blocked because its address partially overlapped with an older store.",
"EventCode":"0x03",
"EventName":"LD_BLOCKS.STORE_FORWARD",
"PEBS":"1",
"SampleAfterValue":"1000003",
"UMask":"0x2",
"Unit":"cpu_atom"
},
{
"BriefDescription":"Cycles Uops delivered by the LSD, but didn't come from the decoder.",
"CounterMask":"1",
"EventCode":"0xa8",
"EventName":"LSD.CYCLES_ACTIVE",
"PublicDescription":"Counts the cycles when at least one uop is delivered by the LSD (Loop-stream detector).",
"SampleAfterValue":"2000003",
"UMask":"0x1",
"Unit":"cpu_core"
},
{
"BriefDescription":"Cycles optimal number of Uops delivered by the LSD, but did not come from the decoder.",
"CounterMask":"6",
"EventCode":"0xa8",
"EventName":"LSD.CYCLES_OK",
"PublicDescription":"Counts the cycles when optimal number of uops is delivered by the LSD (Loop-stream detector).",
"SampleAfterValue":"2000003",
"UMask":"0x1",
"Unit":"cpu_core"
},
{
"BriefDescription":"Number of Uops delivered by the LSD.",
"EventCode":"0xa8",
"EventName":"LSD.UOPS",
"PublicDescription":"Counts the number of uops delivered to the back-end by the LSD(Loop Stream Detector).",
"SampleAfterValue":"2000003",
"UMask":"0x1",
"Unit":"cpu_core"
},
{
"BriefDescription":"Number of machine clears (nukes) of any type.",
"CounterMask":"1",
"EdgeDetect":"1",
"EventCode":"0xc3",
"EventName":"MACHINE_CLEARS.COUNT",
"PublicDescription":"Counts the number of machine clears (nukes) of any type.",
"SampleAfterValue":"100003",
"UMask":"0x1",
"Unit":"cpu_core"
},
{
"BriefDescription":"Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.",
"EventCode":"0xc3",
"EventName":"MACHINE_CLEARS.DISAMBIGUATION",
"SampleAfterValue":"20003",
"UMask":"0x8",
"Unit":"cpu_atom"
},
{
"BriefDescription":"Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs.",
"EventCode":"0xc3",
"EventName":"MACHINE_CLEARS.PAGE_FAULT",
"SampleAfterValue":"20003",
"UMask":"0x20",
"Unit":"cpu_atom"
},
{
"BriefDescription":"Counts the number of machine clears that flush the pipeline and restart the machine with the use of microcode due to SMC, MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_TRAP.",
"EventCode":"0xc3",
"EventName":"MACHINE_CLEARS.SLOW",
"SampleAfterValue":"20003",
"UMask":"0x6f",
"Unit":"cpu_atom"
},
{
"BriefDescription":"Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.",
"EventCode":"0xc3",
"EventName":"MACHINE_CLEARS.SMC",
"SampleAfterValue":"20003",
"UMask":"0x1",
"Unit":"cpu_atom"
},
{
"BriefDescription":"Counts cycles where the pipeline is stalled due to serializing operations.",
"EventCode":"0xa2",
"EventName":"RESOURCE_STALLS.SCOREBOARD",
"SampleAfterValue":"100003",
"UMask":"0x2",
"Unit":"cpu_core"
},
{
"BriefDescription":"This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions.",
"EventCode":"0xa4",
"EventName":"TOPDOWN.BACKEND_BOUND_SLOTS",
"PublicDescription":"This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions.\nThe count is distributed among unhalted logical processors (hyper-threads) who share the same physical core, in processors that support Intel Hyper-Threading Technology. Software can use this event as the numerator for the Backend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.",
"SampleAfterValue":"10000003",
"UMask":"0x2",
"Unit":"cpu_core"
},
{
"BriefDescription":"TMA slots wasted due to incorrect speculations.",
"EventCode":"0xa4",
"EventName":"TOPDOWN.BAD_SPEC_SLOTS",
"PublicDescription":"Number of slots of TMA method that were wasted due to incorrect speculation. It covers all types of control-flow or data-related mis-speculations.",
"SampleAfterValue":"10000003",
"UMask":"0x4",
"Unit":"cpu_core"
},
{
"BriefDescription":"TMA slots wasted due to incorrect speculation by branch mispredictions",
"EventCode":"0xa4",
"EventName":"TOPDOWN.BR_MISPREDICT_SLOTS",
"PublicDescription":"Number of TMA slots that were wasted due to incorrect speculation by (any type of) branch mispredictions. This event estimates number of speculative operations that were issued but not retired as well as the out-of-order engine recovery past a branch misprediction.",
"SampleAfterValue":"10000003",
"UMask":"0x8",
"Unit":"cpu_core"
},
{
"BriefDescription":"TOPDOWN.MEMORY_BOUND_SLOTS",
"EventCode":"0xa4",
"EventName":"TOPDOWN.MEMORY_BOUND_SLOTS",
"SampleAfterValue":"10000003",
"UMask":"0x10",
"Unit":"cpu_core"
},
{
"BriefDescription":"TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
"EventName":"TOPDOWN.SLOTS",
"PublicDescription":"Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
"SampleAfterValue":"10000003",
"UMask":"0x4",
"Unit":"cpu_core"
},
{
"BriefDescription":"TMA slots available for an unhalted logical processor. General counter - architectural event",
"EventCode":"0xa4",
"EventName":"TOPDOWN.SLOTS_P",
"PublicDescription":"Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
"SampleAfterValue":"10000003",
"UMask":"0x1",
"Unit":"cpu_core"
},
{
"BriefDescription":"Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
"EventCode":"0x73",
"EventName":"TOPDOWN_BAD_SPECULATION.ALL",
"PublicDescription":"Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
"SampleAfterValue":"1000003",
"Unit":"cpu_atom"
},
{
"BriefDescription":"Counts the number of issue slots every cycle that were not consumed by the backend due to Fast Nukes such as Memory Ordering Machine clears and MRN nukes",
"EventCode":"0x73",
"EventName":"TOPDOWN_BAD_SPECULATION.FASTNUKE",
"SampleAfterValue":"1000003",
"UMask":"0x2",
"Unit":"cpu_atom"
},
{
"BriefDescription":"Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.",
"BriefDescription":"Counts the number of issue slots every cycle that were not consumed by the backend due to mrbl stall. A 'marble' refers to a physical register file entry, also known as the physical destination (PDST).",
"EventCode":"0x74",
"EventName":"TOPDOWN_BE_BOUND.REGISTER",
"SampleAfterValue":"1000003",
"UMask":"0x20",
"Unit":"cpu_atom"
},
{
"BriefDescription":"Counts the number of issue slots every cycle that were not consumed by the backend due to iq/jeu scoreboards or ms scb",
"BriefDescription":"Counts the number of issue slots every cycle that were not delivered by the frontend due to BAClear",
"EventCode":"0x71",
"EventName":"TOPDOWN_FE_BOUND.BRANCH_DETECT",
"SampleAfterValue":"1000003",
"UMask":"0x2",
"Unit":"cpu_atom"
},
{
"BriefDescription":"Counts the number of issue slots every cycle that were not delivered by the frontend due to BTClear",
"EventCode":"0x71",
"EventName":"TOPDOWN_FE_BOUND.BRANCH_RESTEER",
"SampleAfterValue":"1000003",
"UMask":"0x40",
"Unit":"cpu_atom"
},
{
"BriefDescription":"Counts the number of issue slots every cycle that were not delivered by the frontend due to ms",
"EventCode":"0x71",
"EventName":"TOPDOWN_FE_BOUND.CISC",
"SampleAfterValue":"1000003",
"UMask":"0x1",
"Unit":"cpu_atom"
},
{
"BriefDescription":"Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stall",
"EventCode":"0x71",
"EventName":"TOPDOWN_FE_BOUND.DECODE",
"SampleAfterValue":"1000003",
"UMask":"0x8",
"Unit":"cpu_atom"
},
{
"BriefDescription":"Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.",
"BriefDescription":"Counts the number of issue slots every cycle that were not delivered by the frontend due to latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.",
"EventCode":"0x71",
"EventName":"TOPDOWN_FE_BOUND.FRONTEND_LATENCY",
"SampleAfterValue":"1000003",
"UMask":"0x72",
"Unit":"cpu_atom"
},
{
"BriefDescription":"This event is deprecated. [This event is alias to TOPDOWN_FE_BOUND.ITLB_MISS]",
"Deprecated":"1",
"EventCode":"0x71",
"EventName":"TOPDOWN_FE_BOUND.ITLB",
"SampleAfterValue":"1000003",
"UMask":"0x10",
"Unit":"cpu_atom"
},
{
"BriefDescription":"Counts the number of issue slots every cycle that were not delivered by the frontend due to itlb miss [This event is alias to TOPDOWN_FE_BOUND.ITLB]",
"EventCode":"0x71",
"EventName":"TOPDOWN_FE_BOUND.ITLB_MISS",
"SampleAfterValue":"1000003",
"UMask":"0x10",
"Unit":"cpu_atom"
},
{
"BriefDescription":"Counts the number of issue slots every cycle that were not delivered by the frontend due to predecode wrong",
"BriefDescription":"Number of non dec-by-all uops decoded by decoder",
"EventCode":"0x76",
"EventName":"UOPS_DECODED.DEC0_UOPS",
"PublicDescription":"This event counts the number of not dec-by-all uops decoded by decoder 0.",
"SampleAfterValue":"1000003",
"UMask":"0x1",
"Unit":"cpu_core"
},
{
"BriefDescription":"Uops executed on port 0",
"EventCode":"0xb2",
"EventName":"UOPS_DISPATCHED.PORT_0",
"PublicDescription":"Number of uops dispatch to execution port 0.",
"SampleAfterValue":"2000003",
"UMask":"0x1",
"Unit":"cpu_core"
},
{
"BriefDescription":"Uops executed on port 1",
"EventCode":"0xb2",
"EventName":"UOPS_DISPATCHED.PORT_1",
"PublicDescription":"Number of uops dispatch to execution port 1.",
"SampleAfterValue":"2000003",
"UMask":"0x2",
"Unit":"cpu_core"
},
{
"BriefDescription":"Uops executed on ports 2, 3 and 10",
"EventCode":"0xb2",
"EventName":"UOPS_DISPATCHED.PORT_2_3_10",
"PublicDescription":"Number of uops dispatch to execution ports 2, 3 and 10",
"SampleAfterValue":"2000003",
"UMask":"0x4",
"Unit":"cpu_core"
},
{
"BriefDescription":"Uops executed on ports 4 and 9",
"EventCode":"0xb2",
"EventName":"UOPS_DISPATCHED.PORT_4_9",
"PublicDescription":"Number of uops dispatch to execution ports 4 and 9",
"SampleAfterValue":"2000003",
"UMask":"0x10",
"Unit":"cpu_core"
},
{
"BriefDescription":"Uops executed on ports 5 and 11",
"EventCode":"0xb2",
"EventName":"UOPS_DISPATCHED.PORT_5_11",
"PublicDescription":"Number of uops dispatch to execution ports 5 and 11",
"SampleAfterValue":"2000003",
"UMask":"0x20",
"Unit":"cpu_core"
},
{
"BriefDescription":"Uops executed on port 6",
"EventCode":"0xb2",
"EventName":"UOPS_DISPATCHED.PORT_6",
"PublicDescription":"Number of uops dispatch to execution port 6.",
"SampleAfterValue":"2000003",
"UMask":"0x40",
"Unit":"cpu_core"
},
{
"BriefDescription":"Uops executed on ports 7 and 8",
"EventCode":"0xb2",
"EventName":"UOPS_DISPATCHED.PORT_7_8",
"PublicDescription":"Number of uops dispatch to execution ports 7 and 8.",
"SampleAfterValue":"2000003",
"UMask":"0x80",
"Unit":"cpu_core"
},
{
"BriefDescription":"Number of uops executed on the core.",
"EventCode":"0xb1",
"EventName":"UOPS_EXECUTED.CORE",
"PublicDescription":"Counts the number of uops executed from any thread.",
"SampleAfterValue":"2000003",
"UMask":"0x2",
"Unit":"cpu_core"
},
{
"BriefDescription":"Cycles at least 1 micro-op is executed from any thread on physical core.",
"CounterMask":"1",
"EventCode":"0xb1",
"EventName":"UOPS_EXECUTED.CORE_CYCLES_GE_1",
"PublicDescription":"Counts cycles when at least 1 micro-op is executed from any thread on physical core.",
"SampleAfterValue":"2000003",
"UMask":"0x2",
"Unit":"cpu_core"
},
{
"BriefDescription":"Cycles at least 2 micro-op is executed from any thread on physical core.",
"CounterMask":"2",
"EventCode":"0xb1",
"EventName":"UOPS_EXECUTED.CORE_CYCLES_GE_2",
"PublicDescription":"Counts cycles when at least 2 micro-ops are executed from any thread on physical core.",
"SampleAfterValue":"2000003",
"UMask":"0x2",
"Unit":"cpu_core"
},
{
"BriefDescription":"Cycles at least 3 micro-op is executed from any thread on physical core.",
"CounterMask":"3",
"EventCode":"0xb1",
"EventName":"UOPS_EXECUTED.CORE_CYCLES_GE_3",
"PublicDescription":"Counts cycles when at least 3 micro-ops are executed from any thread on physical core.",
"SampleAfterValue":"2000003",
"UMask":"0x2",
"Unit":"cpu_core"
},
{
"BriefDescription":"Cycles at least 4 micro-op is executed from any thread on physical core.",
"CounterMask":"4",
"EventCode":"0xb1",
"EventName":"UOPS_EXECUTED.CORE_CYCLES_GE_4",
"PublicDescription":"Counts cycles when at least 4 micro-ops are executed from any thread on physical core.",
"SampleAfterValue":"2000003",
"UMask":"0x2",
"Unit":"cpu_core"
},
{
"BriefDescription":"Cycles where at least 1 uop was executed per-thread",
"CounterMask":"1",
"EventCode":"0xb1",
"EventName":"UOPS_EXECUTED.CYCLES_GE_1",
"PublicDescription":"Cycles where at least 1 uop was executed per-thread.",
"SampleAfterValue":"2000003",
"UMask":"0x1",
"Unit":"cpu_core"
},
{
"BriefDescription":"Cycles where at least 2 uops were executed per-thread",
"CounterMask":"2",
"EventCode":"0xb1",
"EventName":"UOPS_EXECUTED.CYCLES_GE_2",
"PublicDescription":"Cycles where at least 2 uops were executed per-thread.",
"SampleAfterValue":"2000003",
"UMask":"0x1",
"Unit":"cpu_core"
},
{
"BriefDescription":"Cycles where at least 3 uops were executed per-thread",
"CounterMask":"3",
"EventCode":"0xb1",
"EventName":"UOPS_EXECUTED.CYCLES_GE_3",
"PublicDescription":"Cycles where at least 3 uops were executed per-thread.",
"SampleAfterValue":"2000003",
"UMask":"0x1",
"Unit":"cpu_core"
},
{
"BriefDescription":"Cycles where at least 4 uops were executed per-thread",
"CounterMask":"4",
"EventCode":"0xb1",
"EventName":"UOPS_EXECUTED.CYCLES_GE_4",
"PublicDescription":"Cycles where at least 4 uops were executed per-thread.",
"SampleAfterValue":"2000003",
"UMask":"0x1",
"Unit":"cpu_core"
},
{
"BriefDescription":"Counts number of cycles no uops were dispatched to be executed on this thread.",
"CounterMask":"1",
"EventCode":"0xb1",
"EventName":"UOPS_EXECUTED.STALLS",
"Invert":"1",
"PublicDescription":"Counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread.",
"SampleAfterValue":"2000003",
"UMask":"0x1",
"Unit":"cpu_core"
},
{
"BriefDescription":"Counts the number of uops to be executed per-thread each cycle.",
"EventCode":"0xb1",
"EventName":"UOPS_EXECUTED.THREAD",
"SampleAfterValue":"2000003",
"UMask":"0x1",
"Unit":"cpu_core"
},
{
"BriefDescription":"Counts the number of x87 uops dispatched.",
"EventCode":"0xb1",
"EventName":"UOPS_EXECUTED.X87",
"PublicDescription":"Counts the number of x87 uops executed.",
"SampleAfterValue":"2000003",
"UMask":"0x10",
"Unit":"cpu_core"
},
{
"BriefDescription":"Counts the number of uops issued by the front end every cycle.",
"EventCode":"0x0e",
"EventName":"UOPS_ISSUED.ANY",
"PublicDescription":"Counts the number of uops issued by the front end every cycle. When 4-uops are requested and only 2-uops are delivered, the event counts 2. Uops_issued correlates to the number of ROB entries. If uop takes 2 ROB slots it counts as 2 uops_issued.",
"SampleAfterValue":"1000003",
"Unit":"cpu_atom"
},
{
"BriefDescription":"Uops that RAT issues to RS",
"EventCode":"0xae",
"EventName":"UOPS_ISSUED.ANY",
"PublicDescription":"Counts the number of uops that the Resource Allocation Table (RAT) issues to the Reservation Station (RS).",
"SampleAfterValue":"2000003",
"UMask":"0x1",
"Unit":"cpu_core"
},
{
"BriefDescription":"UOPS_ISSUED.CYCLES",
"CounterMask":"1",
"EventCode":"0xae",
"EventName":"UOPS_ISSUED.CYCLES",
"SampleAfterValue":"2000003",
"UMask":"0x1",
"Unit":"cpu_core"
},
{
"BriefDescription":"Cycles when RAT does not issue Uops to RS for the thread",
"CounterMask":"1",
"EventCode":"0xae",
"EventName":"UOPS_ISSUED.STALLS",
"Invert":"1",
"PublicDescription":"Counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.",
"SampleAfterValue":"1000003",
"UMask":"0x1",
"Unit":"cpu_core"
},
{
"BriefDescription":"Retired uops except the last uop of each instruction.",
"EventCode":"0xc2",
"EventName":"UOPS_RETIRED.HEAVY",
"PublicDescription":"Counts the number of retired micro-operations (uops) except the last uop of each instruction. An instruction that is decoded into less than two uops does not contribute to the count.",
"SampleAfterValue":"2000003",
"UMask":"0x1",
"Unit":"cpu_core"
},
{
"BriefDescription":"Counts the number of integer divide uops retired.",
"EventCode":"0xc2",
"EventName":"UOPS_RETIRED.IDIV",
"PEBS":"1",
"SampleAfterValue":"2000003",
"UMask":"0x10",
"Unit":"cpu_atom"
},
{
"BriefDescription":"Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.",
"EventCode":"0xc2",
"EventName":"UOPS_RETIRED.MS",
"PEBS":"1",
"SampleAfterValue":"2000003",
"UMask":"0x1",
"Unit":"cpu_atom"
},
{
"BriefDescription":"UOPS_RETIRED.MS",
"EventCode":"0xc2",
"EventName":"UOPS_RETIRED.MS",
"MSRIndex":"0x3F7",
"MSRValue":"0x8",
"SampleAfterValue":"2000003",
"UMask":"0x4",
"Unit":"cpu_core"
},
{
"BriefDescription":"This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric.",
"EventCode":"0xc2",
"EventName":"UOPS_RETIRED.SLOTS",
"PublicDescription":"This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance for example, as measured by the instructions-per-cycle metric.\nSoftware can use this event as the numerator for the Retiring metric (or top-level category) of the Top-down Microarchitecture Analysis method.",
"SampleAfterValue":"2000003",
"UMask":"0x2",
"Unit":"cpu_core"
},
{
"BriefDescription":"Cycles with less than 10 actually retired uops.",
"CounterMask":"10",
"EventCode":"0xc2",
"EventName":"UOPS_RETIRED.TOTAL_CYCLES",
"Invert":"1",
"PublicDescription":"Counts the number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.",
"SampleAfterValue":"1000003",
"UMask":"0x2",
"Unit":"cpu_core"
},
{
"BriefDescription":"Counts the number of x87 uops retired, includes those in ms flows",
