105 lines
2.5 KiB
YAML
105 lines
2.5 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/arm/arm,coresight-stm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Arm CoreSight System Trace MacroCell
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maintainers:
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- Mathieu Poirier <mathieu.poirier@linaro.org>
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- Mike Leach <mike.leach@linaro.org>
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- Leo Yan <leo.yan@linaro.org>
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- Suzuki K Poulose <suzuki.poulose@arm.com>
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description: |
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CoreSight components are compliant with the ARM CoreSight architecture
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specification and can be connected in various topologies to suit a particular
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SoCs tracing needs. These trace components can generally be classified as
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sinks, links and sources. Trace data produced by one or more sources flows
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through the intermediate links connecting the source to the currently selected
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sink.
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The STM is a trace source that is integrated into a CoreSight system, designed
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primarily for high-bandwidth trace of instrumentation embedded into software.
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This instrumentation is made up of memory-mapped writes to the STM Advanced
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eXtensible Interface (AXI) slave, which carry information about the behavior
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of the software.
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select:
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properties:
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compatible:
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contains:
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const: arm,coresight-stm
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required:
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- compatible
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allOf:
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- $ref: /schemas/arm/primecell.yaml#
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properties:
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compatible:
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items:
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- const: arm,coresight-stm
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- const: arm,primecell
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reg:
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maxItems: 2
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reg-names:
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items:
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- const: stm-base
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- const: stm-stimulus-base
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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minItems: 1
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items:
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- const: apb_pclk
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- const: atclk
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power-domains:
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maxItems: 1
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out-ports:
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$ref: /schemas/graph.yaml#/properties/ports
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additionalProperties: false
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properties:
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port:
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description: Output connection to the CoreSight Trace bus.
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$ref: /schemas/graph.yaml#/properties/port
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- out-ports
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unevaluatedProperties: false
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examples:
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- |
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stm@20100000 {
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compatible = "arm,coresight-stm", "arm,primecell";
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reg = <0x20100000 0x1000>,
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<0x28000000 0x180000>;
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reg-names = "stm-base", "stm-stimulus-base";
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clocks = <&soc_smc50mhz>;
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clock-names = "apb_pclk";
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out-ports {
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port {
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stm_out_port: endpoint {
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remote-endpoint = <&main_funnel_in_port2>;
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};
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};
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};
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};
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...
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