2023-08-30 17:31:07 +02:00
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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2023-10-24 12:59:35 +02:00
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$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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2023-08-30 17:31:07 +02:00
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title: MediaTek Functional Clock Controller for MT8186
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maintainers:
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- Chun-Jie Chen <chun-jie.chen@mediatek.com>
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description: |
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The clock architecture in MediaTek like below
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PLLs -->
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dividers -->
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muxes
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-->
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clock gate
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The devices provide clock gate control in different IP blocks.
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properties:
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compatible:
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items:
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- enum:
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- mediatek,mt8186-imp_iic_wrap
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- mediatek,mt8186-mfgsys
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- mediatek,mt8186-wpesys
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- mediatek,mt8186-imgsys1
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- mediatek,mt8186-imgsys2
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- mediatek,mt8186-vdecsys
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- mediatek,mt8186-vencsys
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- mediatek,mt8186-camsys
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- mediatek,mt8186-camsys_rawa
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- mediatek,mt8186-camsys_rawb
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- mediatek,mt8186-mdpsys
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- mediatek,mt8186-ipesys
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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imp_iic_wrap: clock-controller@11017000 {
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compatible = "mediatek,mt8186-imp_iic_wrap";
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reg = <0x11017000 0x1000>;
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#clock-cells = <1>;
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};
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