2023-08-30 17:31:07 +02:00
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/ata/snps,dwc-ahci-common.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Synopsys DWC AHCI SATA controller properties
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maintainers:
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- Serge Semin <fancer.lancer@gmail.com>
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description:
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This document defines device tree schema for the generic Synopsys DWC
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AHCI controller properties.
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select: false
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allOf:
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- $ref: ahci-common.yaml#
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properties:
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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description:
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Basic DWC AHCI SATA clock sources like application AXI/AHB BIU clock,
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PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx)
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clock, etc.
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minItems: 1
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maxItems: 6
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clock-names:
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minItems: 1
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maxItems: 6
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items:
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oneOf:
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- description: Application APB/AHB/AXI BIU clock
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enum:
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- pclk
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- aclk
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- hclk
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- sata
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- description: Power Module keep-alive clock
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const: pmalive
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- description: RxOOB detection clock
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const: rxoob
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- description: PHY Transmit Clock
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const: asic
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- description: PHY Receive Clock
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const: rbc
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- description: SATA Ports reference clock
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const: ref
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resets:
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description:
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At least basic application and reference clock domains resets are
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normally supported by the DWC AHCI SATA controller.
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minItems: 1
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maxItems: 4
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reset-names:
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minItems: 1
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maxItems: 4
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items:
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oneOf:
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- description: Application AHB/AXI BIU clock domain reset control
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enum:
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- arst
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- hrst
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- description: Power Module keep-alive clock domain reset control
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const: pmalive
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- description: RxOOB detection clock domain reset control
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const: rxoob
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- description: Reference clock domain reset control
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const: ref
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patternProperties:
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"^sata-port@[0-9a-e]$":
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$ref: '#/$defs/dwc-ahci-port'
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additionalProperties: true
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$defs:
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dwc-ahci-port:
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$ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port
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properties:
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reg:
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minimum: 0
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maximum: 7
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snps,tx-ts-max:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Maximal size of Tx DMA transactions in FIFO words
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enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ]
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snps,rx-ts-max:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Maximal size of Rx DMA transactions in FIFO words
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enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ]
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...
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