81 lines
1.9 KiB
YAML
81 lines
1.9 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/mediatek,mt7621-sysc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MT7621 Clock
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maintainers:
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- Sergio Paracuellos <sergio.paracuellos@gmail.com>
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description: |
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The MT7621 has a PLL controller from where the cpu clock is provided
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as well as derived clocks for the bus and the peripherals. It also
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can gate SoC device clocks.
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Each clock is assigned an identifier and client nodes use this identifier
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to specify the clock which they consume.
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All these identifiers could be found in:
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[1]: <include/dt-bindings/clock/mt7621-clk.h>.
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The clocks are provided inside a system controller node.
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This node is also a reset provider for all the peripherals.
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Reset related bits are defined in:
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[2]: <include/dt-bindings/reset/mt7621-reset.h>.
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properties:
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compatible:
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items:
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- const: mediatek,mt7621-sysc
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- const: syscon
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reg:
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maxItems: 1
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"#clock-cells":
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description:
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The first cell indicates the clock number, see [1] for available
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clocks.
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const: 1
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"#reset-cells":
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description:
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The first cell indicates the reset bit within the register, see
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[2] for available resets.
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const: 1
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ralink,memctl:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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phandle of syscon used to control memory registers
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clock-output-names:
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maxItems: 8
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required:
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- compatible
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- reg
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- '#clock-cells'
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- ralink,memctl
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mt7621-clk.h>
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sysc: sysc@0 {
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compatible = "mediatek,mt7621-sysc", "syscon";
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reg = <0x0 0x100>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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ralink,memctl = <&memc>;
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clock-output-names = "xtal", "cpu", "bus",
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"50m", "125m", "150m",
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"250m", "270m";
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};
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