2023-08-30 17:31:07 +02:00
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/mediatek/mediatek,merge.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek display merge
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maintainers:
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- Chun-Kuang Hu <chunkuang.hu@kernel.org>
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- Philipp Zabel <p.zabel@pengutronix.de>
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description: |
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Mediatek display merge, namely MERGE, is used to merge two slice-per-line
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inputs into one side-by-side output.
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MERGE device node must be siblings to the central MMSYS_CONFIG node.
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For a description of the MMSYS_CONFIG binding, see
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Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
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for details.
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properties:
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compatible:
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oneOf:
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2023-10-24 12:59:35 +02:00
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- enum:
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- mediatek,mt8173-disp-merge
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- mediatek,mt8195-disp-merge
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2023-08-30 17:31:07 +02:00
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- items:
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2023-10-24 12:59:35 +02:00
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- const: mediatek,mt6795-disp-merge
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2023-08-30 17:31:07 +02:00
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- const: mediatek,mt8173-disp-merge
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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power-domains:
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description: A phandle and PM domain specifier as defined by bindings of
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the power controller specified by phandle. See
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Documentation/devicetree/bindings/power/power-domain.yaml for details.
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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oneOf:
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- items:
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- const: merge
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- items:
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- const: merge
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- const: merge_async
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mediatek,merge-fifo-en:
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description:
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The setting of merge fifo is mainly provided for the display latency
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buffer to ensure that the back-end panel display data will not be
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underrun, a little more data is needed in the fifo.
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According to the merge fifo settings, when the water level is detected
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to be insufficient, it will trigger RDMA sending ultra and preulra
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command to SMI to speed up the data rate.
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type: boolean
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mediatek,merge-mute:
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description: Support mute function. Mute the content of merge output.
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type: boolean
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mediatek,gce-client-reg:
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description: The register of client driver can be configured by gce with
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4 arguments defined in this property, such as phandle of gce, subsys id,
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register offset and size. Each GCE subsys id is mapping to a client
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defined in the header include/dt-bindings/gce/<chip>-gce.h.
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$ref: /schemas/types.yaml#/definitions/phandle-array
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maxItems: 1
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resets:
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description: reset controller
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See Documentation/devicetree/bindings/reset/reset.txt for details.
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maxItems: 1
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required:
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- compatible
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- reg
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- power-domains
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- clocks
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <dt-bindings/power/mt8173-power.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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merge@14017000 {
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compatible = "mediatek,mt8173-disp-merge";
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reg = <0 0x14017000 0 0x1000>;
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power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_DISP_MERGE>;
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clock-names = "merge";
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};
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};
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