2023-08-30 17:31:07 +02:00
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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# Copyright 2019 Texas Instruments Incorporated
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%YAML 1.2
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---
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2023-10-24 12:59:35 +02:00
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$id: http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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2023-08-30 17:31:07 +02:00
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title: Texas Instruments AM65x Display Subsystem
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maintainers:
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- Jyri Sarha <jsarha@ti.com>
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- Tomi Valkeinen <tomi.valkeinen@ti.com>
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description: |
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The AM65x TI Keystone Display SubSystem with two output ports and
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two video planes. The first video port supports OLDI and the second
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supports DPI format. The fist plane is full video plane with all
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features and the second is a "lite plane" without scaling support.
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properties:
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compatible:
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const: ti,am65x-dss
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reg:
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description:
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Addresses to each DSS memory region described in the SoC's TRM.
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items:
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- description: common DSS register area
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- description: VIDL1 light video plane
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- description: VID video plane
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- description: OVR1 overlay manager for vp1
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- description: OVR2 overlay manager for vp2
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- description: VP1 video port 1
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- description: VP2 video port 2
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reg-names:
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items:
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- const: common
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- const: vidl1
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- const: vid
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- const: ovr1
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- const: ovr2
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- const: vp1
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- const: vp2
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clocks:
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items:
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- description: fck DSS functional clock
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- description: vp1 Video Port 1 pixel clock
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- description: vp2 Video Port 2 pixel clock
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clock-names:
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items:
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- const: fck
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- const: vp1
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- const: vp2
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assigned-clocks:
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minItems: 1
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maxItems: 3
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assigned-clock-parents:
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minItems: 1
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maxItems: 3
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interrupts:
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maxItems: 1
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power-domains:
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maxItems: 1
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description: phandle to the associated power domain
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dma-coherent:
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type: boolean
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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The DSS OLDI output port node form video port 1
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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The DSS DPI output port node from video port 2
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ti,am65x-oldi-io-ctrl:
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2023-10-24 12:59:35 +02:00
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$ref: /schemas/types.yaml#/definitions/phandle
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2023-08-30 17:31:07 +02:00
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description:
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phandle to syscon device node mapping OLDI IO_CTRL registers.
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The mapped range should point to OLDI_DAT0_IO_CTRL, map it and
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following OLDI_DAT1_IO_CTRL, OLDI_DAT2_IO_CTRL, OLDI_DAT3_IO_CTRL,
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and OLDI_CLK_IO_CTRL registers. This property is needed for OLDI
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interface to work.
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max-memory-bandwidth:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Input memory (from main memory to dispc) bandwidth limit in
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bytes per second
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- interrupts
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- ports
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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dss: dss@4a00000 {
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compatible = "ti,am65x-dss";
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reg = <0x04a00000 0x1000>, /* common */
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<0x04a02000 0x1000>, /* vidl1 */
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<0x04a06000 0x1000>, /* vid */
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<0x04a07000 0x1000>, /* ovr1 */
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<0x04a08000 0x1000>, /* ovr2 */
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<0x04a0a000 0x1000>, /* vp1 */
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<0x04a0b000 0x1000>; /* vp2 */
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reg-names = "common", "vidl1", "vid",
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"ovr1", "ovr2", "vp1", "vp2";
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ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
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power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 67 1>,
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<&k3_clks 216 1>,
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<&k3_clks 67 2>;
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clock-names = "fck", "vp1", "vp2";
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interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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oldi_out0: endpoint {
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remote-endpoint = <&lcd_in0>;
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};
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};
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};
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};
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