2023-08-30 17:31:07 +02:00
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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2023-10-24 12:59:35 +02:00
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$id: http://devicetree.org/schemas/i2c/qcom,i2c-geni-qcom.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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2023-08-30 17:31:07 +02:00
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title: Qualcomm Geni based QUP I2C Controller
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maintainers:
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- Andy Gross <agross@kernel.org>
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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properties:
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compatible:
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enum:
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- qcom,geni-i2c
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- qcom,geni-i2c-master-hub
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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minItems: 1
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maxItems: 2
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clock-frequency:
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default: 100000
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dmas:
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maxItems: 2
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dma-names:
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items:
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- const: tx
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- const: rx
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interconnects:
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minItems: 2
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maxItems: 3
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interconnect-names:
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minItems: 2
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maxItems: 3
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interrupts:
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maxItems: 1
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operating-points-v2: true
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pinctrl-0: true
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pinctrl-1: true
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pinctrl-names:
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minItems: 1
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items:
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- const: default
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- const: sleep
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power-domains:
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maxItems: 1
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reg:
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maxItems: 1
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required-opps:
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maxItems: 1
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required:
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- compatible
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- interrupts
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- clocks
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- clock-names
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- reg
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allOf:
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- $ref: /schemas/i2c/i2c-controller.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: qcom,geni-i2c-master-hub
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then:
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properties:
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clocks:
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minItems: 2
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clock-names:
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items:
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- const: se
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- const: core
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dmas: false
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dma-names: false
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interconnects:
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maxItems: 2
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interconnect-names:
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items:
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- const: qup-core
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- const: qup-config
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else:
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properties:
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clocks:
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maxItems: 1
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clock-names:
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const: se
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interconnects:
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minItems: 3
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interconnect-names:
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items:
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- const: qup-core
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- const: qup-config
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- const: qup-memory
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-sc7180.h>
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#include <dt-bindings/interconnect/qcom,sc7180.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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i2c@88000 {
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compatible = "qcom,geni-i2c";
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reg = <0x00880000 0x4000>;
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clock-names = "se";
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clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_i2c0_default>;
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interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
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<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
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<&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
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interconnect-names = "qup-core", "qup-config", "qup-memory";
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power-domains = <&rpmhpd SC7180_CX>;
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required-opps = <&rpmhpd_opp_low_svs>;
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};
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...
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