132 lines
3.3 KiB
YAML
132 lines
3.3 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iio/imu/adi,adis16480.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Analog Devices ADIS16480 and similar IMUs
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maintainers:
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- Alexandru Tachici <alexandru.tachici@analog.com>
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properties:
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compatible:
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enum:
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- adi,adis16375
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- adi,adis16480
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- adi,adis16485
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- adi,adis16488
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- adi,adis16490
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- adi,adis16495-1
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- adi,adis16495-2
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- adi,adis16495-3
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- adi,adis16497-1
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- adi,adis16497-2
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- adi,adis16497-3
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reg:
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maxItems: 1
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interrupts:
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minItems: 1
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maxItems: 2
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description: |
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Accepted interrupt types are:
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* IRQ_TYPE_EDGE_RISING
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* IRQ_TYPE_EDGE_FALLING
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interrupt-names:
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minItems: 1
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maxItems: 2
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description:
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Default if not supplied is DIO1.
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items:
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enum:
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- DIO1
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- DIO2
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- DIO3
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- DIO4
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spi-cpha: true
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spi-cpol: true
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reset-gpios:
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maxItems: 1
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description: Connected to RESET pin which is active low.
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clocks:
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maxItems: 1
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description: If not provided, then the internal clock is used.
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clock-names:
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description: |
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sync: In sync mode, the internal clock is disabled and the frequency
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of the external clock signal establishes therate of data
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collection and processing. See Fig 14 and 15 in the datasheet.
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The clock-frequency must be:
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* 3000 to 4500 Hz for adis1649x devices.
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* 700 to 2400 Hz for adis1648x devices.
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pps: In Pulse Per Second (PPS) Mode, the rate of data collection and
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production is equal to the product of the external clock
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frequency and the scale factor in the SYNC_SCALE register, see
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Table 154 in the datasheet.
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The clock-frequency must be:
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* 1 to 128 Hz for adis1649x devices.
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* This mode is not supported by adis1648x devices.
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enum:
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- sync
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- pps
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adi,ext-clk-pin:
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$ref: /schemas/types.yaml#/definitions/string
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description: |
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The DIOx line to be used as an external clock input.
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Each DIOx pin supports only one function at a time (data ready line
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selection or external clock input). When a single pin has two
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two assignments, the enable bit for the lower priority function
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automatically resets to zero (disabling the lower priority function).
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Data ready has highest priority.
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If not provided then DIO2 is assigned as default external clock
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input pin.
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enum:
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- DIO1
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- DIO2
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- DIO3
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- DIO4
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required:
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- compatible
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- reg
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- interrupts
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- spi-cpha
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- spi-cpol
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- spi-max-frequency
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allOf:
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- $ref: /schemas/spi/spi-peripheral-props.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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imu@0 {
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compatible = "adi,adis16495-1";
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reg = <0>;
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spi-max-frequency = <3200000>;
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spi-cpol;
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spi-cpha;
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interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
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interrupt-parent = <&gpio>;
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interrupt-names = "DIO2";
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clocks = <&adis16495_sync>;
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clock-names = "sync";
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adi,ext-clk-pin = "DIO1";
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};
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};
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...
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