2023-08-30 17:31:07 +02:00
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/actions,owl-sirq.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Actions Semi Owl SoCs SIRQ interrupt controller
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maintainers:
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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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- Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
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description: |
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This interrupt controller is found in the Actions Semi Owl SoCs (S500, S700
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and S900) and provides support for handling up to 3 external interrupt lines.
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properties:
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compatible:
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enum:
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- actions,s500-sirq
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- actions,s700-sirq
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- actions,s900-sirq
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reg:
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maxItems: 1
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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description:
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The first cell is the input IRQ number, between 0 and 2, while the second
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cell is the trigger type as defined in interrupt.txt in this directory.
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2023-10-24 12:59:35 +02:00
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interrupts:
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2023-08-30 17:31:07 +02:00
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description: |
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Contains the GIC SPI IRQs mapped to the external interrupt lines.
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They shall be specified sequentially from output 0 to 2.
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minItems: 3
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maxItems: 3
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required:
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- compatible
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- reg
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- interrupt-controller
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- '#interrupt-cells'
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2023-10-24 12:59:35 +02:00
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- interrupts
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2023-08-30 17:31:07 +02:00
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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sirq: interrupt-controller@b01b0200 {
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compatible = "actions,s500-sirq";
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reg = <0xb01b0200 0x4>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ0 */
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* SIRQ1 */
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; /* SIRQ2 */
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};
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...
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