37 lines
1.3 KiB
Plaintext
37 lines
1.3 KiB
Plaintext
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Marvell SEI (System Error Interrupt) Controller
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Marvell SEI (System Error Interrupt) controller is an interrupt
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aggregator. It receives interrupts from several sources and aggregates
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them to a single interrupt line (an SPI) on the parent interrupt
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controller.
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This interrupt controller can handle up to 64 SEIs, a set comes from the
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AP and is wired while a second set comes from the CPs by the mean of
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MSIs.
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Required properties:
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- compatible: should be one of:
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* "marvell,ap806-sei"
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- reg: SEI registers location and length.
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- interrupts: identifies the parent IRQ that will be triggered.
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- #interrupt-cells: number of cells to define an SEI wired interrupt
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coming from the AP, should be 1. The cell is the IRQ
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number.
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- interrupt-controller: identifies the node as an interrupt controller
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for AP interrupts.
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- msi-controller: identifies the node as an MSI controller for the CPs
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interrupts.
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Example:
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sei: interrupt-controller@3f0200 {
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compatible = "marvell,ap806-sei";
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reg = <0x3f0200 0x40>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <1>;
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interrupt-controller;
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msi-controller;
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};
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