2023-08-30 17:31:07 +02:00
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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2023-10-24 12:59:35 +02:00
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$id: http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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2023-08-30 17:31:07 +02:00
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title: Microsemi Ocelot SoC ICPU Interrupt Controller
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maintainers:
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- Alexandre Belloni <alexandre.belloni@bootlin.com>
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allOf:
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- $ref: /schemas/interrupt-controller.yaml#
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description: |
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the Microsemi Ocelot interrupt controller that is part of the
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ICPU. It is connected directly to the MIPS core interrupt
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controller.
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properties:
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compatible:
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items:
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- enum:
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- mscc,jaguar2-icpu-intr
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- mscc,luton-icpu-intr
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- mscc,ocelot-icpu-intr
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- mscc,serval-icpu-intr
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'#interrupt-cells':
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const: 1
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'#address-cells':
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const: 0
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interrupt-controller: true
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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required:
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- compatible
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- '#interrupt-cells'
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- '#address-cells'
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- interrupt-controller
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- reg
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additionalProperties: false
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examples:
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- |
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intc: interrupt-controller@70000070 {
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compatible = "mscc,ocelot-icpu-intr";
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reg = <0x70000070 0x70>;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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interrupt-controller;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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};
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...
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