108 lines
3.6 KiB
YAML
108 lines
3.6 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Texas Instruments K3 Interrupt Router
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maintainers:
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- Lokesh Vutla <lokeshvutla@ti.com>
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allOf:
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- $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
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description: |
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The Interrupt Router (INTR) module provides a mechanism to mux M
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interrupt inputs to N interrupt outputs, where all M inputs are selectable
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to be driven per N output. An Interrupt Router can either handle edge
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triggered or level triggered interrupts and that is fixed in hardware.
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Interrupt Router
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+----------------------+
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| Inputs Outputs |
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+-------+ | +------+ +-----+ |
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| GPIO |----------->| | irq0 | | 0 | | Host IRQ
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+-------+ | +------+ +-----+ | controller
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| . . | +-------+
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+-------+ | . . |----->| IRQ |
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| INTA |----------->| . . | +-------+
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+-------+ | . +-----+ |
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| +------+ | N | |
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| | irqM | +-----+ |
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| +------+ |
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+----------------------+
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There is one register per output (MUXCNTL_N) that controls the selection.
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Configuration of these MUXCNTL_N registers is done by a system controller
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(like the Device Memory and Security Controller on K3 AM654 SoC). System
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controller will keep track of the used and unused registers within the Router.
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Driver should request the system controller to get the range of GIC IRQs
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assigned to the requesting hosts. It is the drivers responsibility to keep
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track of Host IRQs.
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Communication between the host processor running an OS and the system
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controller happens through a protocol called TI System Control Interface
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(TISCI protocol).
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properties:
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compatible:
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const: ti,sci-intr
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ti,intr-trigger-type:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [1, 4]
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description: |
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Should be one of the following.
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1 = If intr supports edge triggered interrupts.
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4 = If intr supports level triggered interrupts.
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reg:
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maxItems: 1
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interrupt-controller: true
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'#interrupt-cells':
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const: 1
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description: |
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The 1st cell should contain interrupt router input hw number.
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ti,interrupt-ranges:
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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description: |
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Interrupt ranges that converts the INTR output hw irq numbers
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to parents's input interrupt numbers.
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items:
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items:
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- description: |
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"output_irq" specifies the base for intr output irq
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- description: |
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"parent's input irq" specifies the base for parent irq
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- description: |
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"limit" specifies the limit for translation
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required:
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- compatible
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- ti,intr-trigger-type
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- interrupt-controller
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- '#interrupt-cells'
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- ti,sci
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- ti,sci-dev-id
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- ti,interrupt-ranges
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unevaluatedProperties: false
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examples:
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- |
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main_gpio_intr: interrupt-controller0 {
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compatible = "ti,sci-intr";
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ti,intr-trigger-type = <1>;
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interrupt-controller;
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interrupt-parent = <&gic500>;
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#interrupt-cells = <1>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <131>;
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ti,interrupt-ranges = <0 360 32>;
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};
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