2023-08-30 17:31:07 +02:00
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iommu/renesas,ipmmu-vmsa.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas VMSA-Compatible IOMMU
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maintainers:
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- Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
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description:
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The IPMMU is an IOMMU implementation compatible with the ARM VMSA page tables.
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It provides address translation for bus masters outside of the CPU, each
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connected to the IPMMU through a port called micro-TLB.
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- renesas,ipmmu-r8a73a4 # R-Mobile APE6
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- renesas,ipmmu-r8a7742 # RZ/G1H
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- renesas,ipmmu-r8a7743 # RZ/G1M
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- renesas,ipmmu-r8a7744 # RZ/G1N
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- renesas,ipmmu-r8a7745 # RZ/G1E
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- renesas,ipmmu-r8a7790 # R-Car H2
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- renesas,ipmmu-r8a7791 # R-Car M2-W
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- renesas,ipmmu-r8a7793 # R-Car M2-N
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- renesas,ipmmu-r8a7794 # R-Car E2
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- const: renesas,ipmmu-vmsa # R-Mobile APE6 or R-Car Gen2 or RZ/G1
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- items:
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- enum:
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- renesas,ipmmu-r8a774a1 # RZ/G2M
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- renesas,ipmmu-r8a774b1 # RZ/G2N
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- renesas,ipmmu-r8a774c0 # RZ/G2E
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- renesas,ipmmu-r8a774e1 # RZ/G2H
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- renesas,ipmmu-r8a7795 # R-Car H3
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- renesas,ipmmu-r8a7796 # R-Car M3-W
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- renesas,ipmmu-r8a77961 # R-Car M3-W+
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- renesas,ipmmu-r8a77965 # R-Car M3-N
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- renesas,ipmmu-r8a77970 # R-Car V3M
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- renesas,ipmmu-r8a77980 # R-Car V3H
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- renesas,ipmmu-r8a77990 # R-Car E3
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- renesas,ipmmu-r8a77995 # R-Car D3
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- items:
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- enum:
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- renesas,ipmmu-r8a779a0 # R-Car V3U
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- renesas,ipmmu-r8a779f0 # R-Car S4-8
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- renesas,ipmmu-r8a779g0 # R-Car V4H
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- const: renesas,rcar-gen4-ipmmu-vmsa # R-Car Gen4
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reg:
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maxItems: 1
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interrupts:
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minItems: 1
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description:
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Specifiers for the MMU fault interrupts. Not required for cache IPMMUs.
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items:
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- description: non-secure mode
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- description: secure mode if supported
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'#iommu-cells':
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const: 1
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description:
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The number of the micro-TLB that the device is connected to.
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power-domains:
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maxItems: 1
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renesas,ipmmu-main:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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2023-10-24 12:59:35 +02:00
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- minItems: 1
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items:
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- description: phandle to main IPMMU
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2023-10-24 12:59:35 +02:00
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- description:
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The interrupt bit number associated with the particular cache
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IPMMU device. If present, the interrupt bit number needs to match
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the main IPMMU IMSSTR register. Only used by cache IPMMU
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instances.
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description:
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2023-10-24 12:59:35 +02:00
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Reference to the main IPMMU.
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2023-08-30 17:31:07 +02:00
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required:
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- compatible
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- reg
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- '#iommu-cells'
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oneOf:
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- required:
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- interrupts
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- required:
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- renesas,ipmmu-main
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additionalProperties: false
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allOf:
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- if:
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properties:
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compatible:
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not:
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contains:
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const: renesas,ipmmu-vmsa
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then:
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required:
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- power-domains
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2023-10-24 12:59:35 +02:00
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- if:
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properties:
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compatible:
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contains:
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const: renesas,rcar-gen4-ipmmu-vmsa
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then:
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properties:
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renesas,ipmmu-main:
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items:
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- maxItems: 1
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else:
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properties:
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renesas,ipmmu-main:
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items:
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- minItems: 2
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2023-08-30 17:31:07 +02:00
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examples:
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- |
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#include <dt-bindings/clock/r8a7791-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/r8a7791-sysc.h>
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ipmmu_mx: iommu@fe951000 {
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compatible = "renesas,ipmmu-r8a7791", "renesas,ipmmu-vmsa";
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reg = <0xfe951000 0x1000>;
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interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
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#iommu-cells = <1>;
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};
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