84 lines
1.9 KiB
YAML
84 lines
1.9 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0-only
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iommu/rockchip,iommu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip IOMMU
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maintainers:
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- Heiko Stuebner <heiko@sntech.de>
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description: |+
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A Rockchip DRM iommu translates io virtual addresses to physical addresses for
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its master device. Each slave device is bound to a single master device and
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shares its clocks, power domain and irq.
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For information on assigning IOMMU controller to its peripheral devices,
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see generic IOMMU bindings.
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properties:
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compatible:
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enum:
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- rockchip,iommu
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- rockchip,rk3568-iommu
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reg:
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items:
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- description: configuration registers for MMU instance 0
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- description: configuration registers for MMU instance 1
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minItems: 1
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interrupts:
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items:
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- description: interruption for MMU instance 0
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- description: interruption for MMU instance 1
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minItems: 1
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clocks:
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items:
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- description: Core clock
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- description: Interface clock
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clock-names:
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items:
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- const: aclk
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- const: iface
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"#iommu-cells":
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const: 0
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power-domains:
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maxItems: 1
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rockchip,disable-mmu-reset:
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$ref: /schemas/types.yaml#/definitions/flag
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description: |
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Do not use the mmu reset operation.
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Some mmu instances may produce unexpected results
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when the reset operation is used.
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- "#iommu-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/rk3399-cru.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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vopl_mmu: iommu@ff940300 {
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compatible = "rockchip,iommu";
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reg = <0xff940300 0x100>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
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clock-names = "aclk", "iface";
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#iommu-cells = <0>;
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};
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