75 lines
2.1 KiB
YAML
75 lines
2.1 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-props.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Common properties for LPDDR types
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description:
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Different LPDDR types generally use the same properties and only differ in the
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range of legal values for each. This file defines the common parts that can be
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reused for each type. Nodes using this schema should generally be nested under
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an LPDDR channel node.
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maintainers:
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- Krzysztof Kozlowski <krzk@kernel.org>
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properties:
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compatible:
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description:
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Compatible strings can be either explicit vendor names and part numbers
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(e.g. elpida,ECB240ABACN), or generated strings of the form
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lpddrX-YY,ZZZZ where X is the LPDDR version, YY is the manufacturer ID
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(from MR5) and ZZZZ is the revision ID (from MR6 and MR7). Both IDs are
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formatted in lower case hexadecimal representation with leading zeroes.
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The latter form can be useful when LPDDR nodes are created at runtime by
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boot firmware that doesn't have access to static part number information.
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reg:
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description:
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The rank number of this LPDDR rank when used as a subnode to an LPDDR
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channel.
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minimum: 0
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maximum: 3
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revision-id:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description:
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Revision IDs read from Mode Register 6 and 7. One byte per uint32 cell (i.e. <MR6 MR7>).
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maxItems: 2
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items:
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minimum: 0
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maximum: 255
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density:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Density in megabits of SDRAM chip. Decoded from Mode Register 8.
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enum:
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- 64
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- 128
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- 256
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- 512
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- 1024
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- 2048
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- 3072
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- 4096
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- 6144
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- 8192
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- 12288
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- 16384
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- 24576
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- 32768
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io-width:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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IO bus width in bits of SDRAM chip. Decoded from Mode Register 8.
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enum:
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- 8
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- 16
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- 32
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additionalProperties: true
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