2023-08-30 17:31:07 +02:00
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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2023-10-24 12:59:35 +02:00
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$id: http://devicetree.org/schemas/memory-controllers/renesas,dbsc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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2023-08-30 17:31:07 +02:00
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title: Renesas DDR Bus Controllers
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maintainers:
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- Geert Uytterhoeven <geert+renesas@glider.be>
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description: |
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Renesas SoCs contain one or more memory controllers. These memory
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controllers differ from one SoC variant to another, and are called by
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different names, e.g. "DDR Bus Controller (DBSC)", "DDR3 Bus State Controller
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(DBSC3)", or "SDRAM Bus State Controller (SBSC)").
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properties:
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compatible:
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enum:
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- renesas,dbsc-r8a73a4 # R-Mobile APE6
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- renesas,dbsc3-r8a7740 # R-Mobile A1
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- renesas,sbsc-sh73a0 # SH-Mobile AG5
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reg:
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maxItems: 1
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interrupts:
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maxItems: 2
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interrupt-names:
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items:
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- const: sec # secure interrupt
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- const: temp # normal (temperature) interrupt
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- power-domains
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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sbsc1: memory-controller@fe400000 {
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compatible = "renesas,sbsc-sh73a0";
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reg = <0xfe400000 0x400>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "sec", "temp";
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power-domains = <&pd_a4bc0>;
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};
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