2023-08-30 17:31:07 +02:00
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/nxp,dwmac-imx.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX8/9 DWMAC glue layer
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maintainers:
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- Clark Wang <xiaoning.wang@nxp.com>
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- Shawn Guo <shawnguo@kernel.org>
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- NXP Linux Team <linux-imx@nxp.com>
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# We need a select here so we don't match all nodes with 'snps,dwmac'
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select:
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properties:
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compatible:
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contains:
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enum:
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- nxp,imx8mp-dwmac-eqos
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- nxp,imx8dxl-dwmac-eqos
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- nxp,imx93-dwmac-eqos
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required:
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- compatible
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allOf:
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2023-10-24 12:59:35 +02:00
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- $ref: snps,dwmac.yaml#
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2023-08-30 17:31:07 +02:00
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- nxp,imx8mp-dwmac-eqos
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- nxp,imx8dxl-dwmac-eqos
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- nxp,imx93-dwmac-eqos
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- const: snps,dwmac-5.10a
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clocks:
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minItems: 3
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items:
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- description: MAC host clock
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- description: MAC apb clock
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- description: MAC timer clock
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- description: MAC RGMII TX clock
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- description: EQOS MEM clock
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clock-names:
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minItems: 3
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maxItems: 5
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contains:
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enum:
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- stmmaceth
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- pclk
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- ptp_ref
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- tx
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- mem
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intf_mode:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: phandle to the GPR syscon
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- description: the offset of the GPR register
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description:
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Should be phandle/offset pair. The phandle to the syscon node which
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encompases the GPR register, and the offset of the GPR register.
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snps,rmii_refclk_ext:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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To select RMII reference clock from external.
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required:
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- compatible
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- clocks
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- clock-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/clock/imx8mp-clock.h>
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eqos: ethernet@30bf0000 {
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compatible = "nxp,imx8mp-dwmac-eqos","snps,dwmac-5.10a";
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reg = <0x30bf0000 0x10000>;
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interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq", "eth_wake_irq";
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clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
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<&clk IMX8MP_CLK_QOS_ENET_ROOT>,
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<&clk IMX8MP_CLK_ENET_QOS_TIMER>,
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<&clk IMX8MP_CLK_ENET_QOS>;
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clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
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phy-mode = "rgmii";
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};
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