81 lines
2.2 KiB
YAML
81 lines
2.2 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0+
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/nxp,tja11xx.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP TJA11xx PHY
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maintainers:
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- Andrew Lunn <andrew@lunn.ch>
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- Florian Fainelli <f.fainelli@gmail.com>
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- Heiner Kallweit <hkallweit1@gmail.com>
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description:
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Bindings for NXP TJA11xx automotive PHYs
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allOf:
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- $ref: ethernet-phy.yaml#
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patternProperties:
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"^ethernet-phy@[0-9a-f]+$":
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type: object
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description: |
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Some packages have multiple PHYs. Secondary PHY should be defines as
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subnode of the first (parent) PHY.
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properties:
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reg:
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minimum: 0
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maximum: 31
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description:
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The ID number for the child PHY. Should be +1 of parent PHY.
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nxp,rmii-refclk-in:
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type: boolean
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description: |
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The REF_CLK is provided for both transmitted and received data
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in RMII mode. This clock signal is provided by the PHY and is
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typically derived from an external 25MHz crystal. Alternatively,
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a 50MHz clock signal generated by an external oscillator can be
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connected to pin REF_CLK. A third option is to connect a 25MHz
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clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
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as input or output according to the actual circuit connection.
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If present, indicates that the REF_CLK will be configured as
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interface reference clock input when RMII mode enabled.
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If not present, the REF_CLK will be configured as interface
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reference clock output when RMII mode enabled.
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Only supported on TJA1100 and TJA1101.
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required:
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- reg
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unevaluatedProperties: false
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examples:
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- |
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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tja1101_phy0: ethernet-phy@4 {
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reg = <0x4>;
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nxp,rmii-refclk-in;
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};
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};
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- |
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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tja1102_phy0: ethernet-phy@4 {
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reg = <0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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tja1102_phy1: ethernet-phy@5 {
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reg = <0x5>;
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};
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};
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};
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