2023-08-30 17:31:07 +02:00
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# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
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# Copyright (C) 2020 Texas Instruments Incorporated
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%YAML 1.2
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---
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2023-10-24 12:59:35 +02:00
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$id: http://devicetree.org/schemas/net/ti,dp83822.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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2023-08-30 17:31:07 +02:00
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title: TI DP83822 ethernet PHY
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maintainers:
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- Andrew Davis <afd@ti.com>
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description: |
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The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
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provides all of the physical layer functions needed to transmit and receive
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data over standard, twisted-pair cables or to connect to an external,
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fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
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connect to a MAC through a standard MII, RMII, or RGMII interface
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Specifications about the Ethernet PHY can be found at:
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http://www.ti.com/lit/ds/symlink/dp83822i.pdf
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allOf:
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2023-10-24 12:59:35 +02:00
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- $ref: ethernet-phy.yaml#
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2023-08-30 17:31:07 +02:00
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properties:
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reg:
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maxItems: 1
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ti,link-loss-low:
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type: boolean
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description: |
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DP83822 PHY in Fiber mode only.
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Sets the DP83822 to detect a link drop condition when the signal goes
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high. If not set then link drop will occur when the signal goes low.
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This property is only applicable if the fiber mode support is strapped
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to on.
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ti,fiber-mode:
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type: boolean
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description: |
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DP83822 PHY only.
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If present the DP83822 PHY is configured to operate in fiber mode
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Fiber mode support can also be strapped. If the strap pin is not set
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correctly or not set at all then this boolean can be used to enable it.
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If the fiber mode is not strapped then signal detection for the PHY
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is disabled.
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In fiber mode, auto-negotiation is disabled and the PHY can only work in
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100base-fx (full and half duplex) modes.
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rx-internal-delay-ps:
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description: |
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DP83822 PHY only.
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Setting this property to a non-zero number sets the RX internal delay
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for the PHY. The internal delay for the PHY is fixed to 3.5ns relative
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to receive data.
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tx-internal-delay-ps:
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description: |
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DP83822 PHY only.
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Setting this property to a non-zero number sets the TX internal delay
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for the PHY. The internal delay for the PHY is fixed to 3.5ns relative
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to transmit data.
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required:
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- reg
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unevaluatedProperties: false
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examples:
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- |
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mdio0 {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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reg = <0>;
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rx-internal-delay-ps = <1>;
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tx-internal-delay-ps = <1>;
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};
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};
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...
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