124 lines
3.1 KiB
YAML
124 lines
3.1 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale i.MX6 PCIe Endpoint controller
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maintainers:
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- Lucas Stach <l.stach@pengutronix.de>
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- Richard Zhu <hongxing.zhu@nxp.com>
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description: |+
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This PCIe controller is based on the Synopsys DesignWare PCIe IP and
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thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
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The controller instances are dual mode where in they can work either in
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Root Port mode or Endpoint mode but one at a time.
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properties:
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compatible:
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enum:
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- fsl,imx8mm-pcie-ep
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- fsl,imx8mq-pcie-ep
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- fsl,imx8mp-pcie-ep
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reg:
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minItems: 2
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reg-names:
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items:
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- const: dbi
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- const: addr_space
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clocks:
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minItems: 3
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items:
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- description: PCIe bridge clock.
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- description: PCIe bus clock.
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- description: PCIe PHY clock.
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- description: Additional required clock entry for imx6sx-pcie,
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imx6sx-pcie-ep, imx8mq-pcie, imx8mq-pcie-ep.
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clock-names:
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minItems: 3
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maxItems: 4
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interrupts:
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items:
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- description: builtin eDMA interrupter.
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interrupt-names:
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items:
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- const: dma
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- interrupt-names
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
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- $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
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- if:
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properties:
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compatible:
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enum:
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- fsl,imx8mq-pcie-ep
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then:
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properties:
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clocks:
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minItems: 4
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clock-names:
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items:
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- const: pcie
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- const: pcie_bus
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- const: pcie_phy
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- const: pcie_aux
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else:
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properties:
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clocks:
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maxItems: 3
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clock-names:
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items:
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- const: pcie
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- const: pcie_bus
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- const: pcie_aux
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8mp-clock.h>
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#include <dt-bindings/power/imx8mp-power.h>
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#include <dt-bindings/reset/imx8mp-reset.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pcie_ep: pcie-ep@33800000 {
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compatible = "fsl,imx8mp-pcie-ep";
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reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>;
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reg-names = "dbi", "addr_space";
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clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
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<&clk IMX8MP_CLK_HSIO_AXI>,
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<&clk IMX8MP_CLK_PCIE_ROOT>;
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clock-names = "pcie", "pcie_bus", "pcie_aux";
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assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
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assigned-clock-rates = <10000000>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
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num-lanes = <1>;
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interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
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interrupt-names = "dma";
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fsl,max-link-speed = <3>;
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power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
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resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
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<&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
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reset-names = "apps", "turnoff";
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phys = <&pcie_phy>;
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phy-names = "pcie-phy";
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num-ib-windows = <4>;
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num-ob-windows = <4>;
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};
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