181 lines
5.4 KiB
YAML
181 lines
5.4 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: HiSilicon Kirin SoCs PCIe host DT description
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maintainers:
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- Xiaowei Song <songxiaowei@hisilicon.com>
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- Binghui Wang <wangbinghui@hisilicon.com>
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description: |
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Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
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It shares common functions with the PCIe DesignWare core driver and
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inherits common properties defined in
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Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie.yaml#
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properties:
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compatible:
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contains:
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enum:
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- hisilicon,kirin960-pcie
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- hisilicon,kirin970-pcie
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reg:
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description: |
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Should contain dbi, apb, config registers location and length.
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For hisilicon,kirin960-pcie, it should also contain phy.
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minItems: 3
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maxItems: 4
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reg-names:
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minItems: 3
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maxItems: 4
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clocks: true
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clock-names:
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items:
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- const: pcie_phy_ref
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- const: pcie_aux
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- const: pcie_apb_phy
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- const: pcie_apb_sys
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- const: pcie_aclk
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phys:
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maxItems: 1
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hisilicon,clken-gpios:
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description: |
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Clock input enablement GPIOs from PCI devices like Ethernet, M.2 and
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mini-PCIe slots.
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required:
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- compatible
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- reg
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- reg-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/hi3660-clock.h>
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#include <dt-bindings/clock/hi3670-clock.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@f4000000 {
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compatible = "hisilicon,kirin960-pcie";
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reg = <0x0 0xf4000000 0x0 0x1000>,
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<0x0 0xff3fe000 0x0 0x1000>,
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<0x0 0xf3f20000 0x0 0x40000>,
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<0x0 0xf5000000 0x0 0x2000>;
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reg-names = "dbi", "apb", "phy", "config";
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bus-range = <0x0 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x02000000 0x0 0x00000000
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0x0 0xf6000000
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0x0 0x02000000>;
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num-lanes = <1>;
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#interrupt-cells = <1>;
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interrupts = <0 283 4>;
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interrupt-names = "msi";
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
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<0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
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<0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
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<0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
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<&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
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<&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
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<&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
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<&crg_ctrl HI3660_ACLK_GATE_PCIE>;
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clock-names = "pcie_phy_ref", "pcie_aux", "pcie_apb_phy",
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"pcie_apb_sys", "pcie_aclk";
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};
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pcie@f5000000 {
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compatible = "hisilicon,kirin970-pcie";
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reg = <0x0 0xf4000000 0x0 0x1000000>,
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<0x0 0xfc180000 0x0 0x1000>,
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<0x0 0xf5000000 0x0 0x2000>;
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reg-names = "dbi", "apb", "config";
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bus-range = <0x0 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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phys = <&pcie_phy>;
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ranges = <0x02000000 0x0 0x00000000
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0x0 0xf6000000
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0x0 0x02000000>;
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num-lanes = <1>;
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#interrupt-cells = <1>;
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interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
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<0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
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<0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
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<0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
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reset-gpios = <&gpio7 0 0>;
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hisilicon,clken-gpios = <&gpio27 3 0>, <&gpio17 0 0>, <&gpio20 6 0>;
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pcie@0,0 { // Lane 0: PCIe switch: Bus 1, Device 0
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reg = <0 0 0 0 0>;
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compatible = "pciclass,0604";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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pcie@0,0 { // Lane 0: upstream
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reg = <0 0 0 0 0>;
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compatible = "pciclass,0604";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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pcie@1,0 { // Lane 4: M.2
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reg = <0x0800 0 0 0 0>;
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compatible = "pciclass,0604";
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device_type = "pci";
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reset-gpios = <&gpio3 1 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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};
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pcie@5,0 { // Lane 5: Mini PCIe
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reg = <0x2800 0 0 0 0>;
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compatible = "pciclass,0604";
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device_type = "pci";
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reset-gpios = <&gpio27 4 0 >;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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};
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pcie@7,0 { // Lane 6: Ethernet
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reg = <0x03800 0 0 0 0>;
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compatible = "pciclass,0604";
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device_type = "pci";
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reset-gpios = <&gpio25 2 0 >;
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#address-cells = <3>;
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#size-cells = <2>;
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ranges;
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};
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};
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};
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};
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};
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