2023-08-30 17:31:07 +02:00
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
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%YAML 1.2
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---
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2023-10-24 12:59:35 +02:00
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$id: http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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2023-08-30 17:31:07 +02:00
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title: CPSW Port's Interface Mode Selection PHY
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maintainers:
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- Kishon Vijay Abraham I <kishon@ti.com>
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description: |
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TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports
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two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
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The interface mode is selected by configuring the MII mode selection register(s)
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(GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and
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bit fields placement in SCM are different between SoCs while fields meaning
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is the same.
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+--------------+
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+-------------------------------+ |SCM |
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| CPSW | | +---------+ |
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| +--------------------------------+gmii_sel | |
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| | | | +---------+ |
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| +----v---+ +--------+ | +--------------+
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| |Port 1..<--+-->GMII/MII<------->
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| | | | | | |
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| +--------+ | +--------+ |
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| | |
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| | +--------+ |
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| | | RMII <------->
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| +--> | |
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| | +--------+ |
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| | |
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| | +--------+ |
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| | | RGMII <------->
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| +--> | |
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| +--------+ |
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+-------------------------------+
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CPSW Port's Interface Mode Selection PHY describes MII interface mode between
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CPSW Port and Ethernet PHY which depends on Eth PHY and board configuration.
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CPSW Port's Interface Mode Selection PHY device should defined as child device
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of SCM node (scm_conf) and can be attached to each CPSW port node using standard
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PHY bindings.
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properties:
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compatible:
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enum:
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- ti,am3352-phy-gmii-sel
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- ti,dra7xx-phy-gmii-sel
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- ti,am43xx-phy-gmii-sel
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- ti,dm814-phy-gmii-sel
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- ti,am654-phy-gmii-sel
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- ti,j7200-cpsw5g-phy-gmii-sel
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- ti,j721e-cpsw9g-phy-gmii-sel
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2023-10-24 12:59:35 +02:00
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- ti,j784s4-cpsw9g-phy-gmii-sel
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2023-08-30 17:31:07 +02:00
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reg:
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maxItems: 1
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'#phy-cells': true
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ti,qsgmii-main-ports:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description: |
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Required only for QSGMII mode. Array to select the port/s for QSGMII
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main mode. The size of the array corresponds to the number of QSGMII
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interfaces and thus, the number of distinct QSGMII main ports,
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supported by the device. If the device supports two QSGMII interfaces
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but only one QSGMII interface is desired, repeat the QSGMII main port
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value corresponding to the QSGMII interface in the array.
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minItems: 1
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maxItems: 2
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items:
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minimum: 1
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maximum: 8
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- ti,dra7xx-phy-gmii-sel
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- ti,dm814-phy-gmii-sel
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- ti,am654-phy-gmii-sel
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- ti,j7200-cpsw5g-phy-gmii-sel
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- ti,j721e-cpsw9g-phy-gmii-sel
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2023-10-24 12:59:35 +02:00
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- ti,j784s4-cpsw9g-phy-gmii-sel
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2023-08-30 17:31:07 +02:00
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then:
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properties:
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'#phy-cells':
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const: 1
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description: CPSW port number (starting from 1)
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- if:
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properties:
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compatible:
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contains:
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enum:
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- ti,j7200-cpsw5g-phy-gmii-sel
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then:
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properties:
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ti,qsgmii-main-ports:
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maxItems: 1
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items:
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minimum: 1
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maximum: 4
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- if:
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properties:
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compatible:
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contains:
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enum:
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- ti,j721e-cpsw9g-phy-gmii-sel
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2023-10-24 12:59:35 +02:00
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- ti,j784s4-cpsw9g-phy-gmii-sel
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2023-08-30 17:31:07 +02:00
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then:
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properties:
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ti,qsgmii-main-ports:
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minItems: 2
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maxItems: 2
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items:
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minimum: 1
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maximum: 8
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- if:
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not:
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properties:
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compatible:
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contains:
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enum:
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- ti,j7200-cpsw5g-phy-gmii-sel
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- ti,j721e-cpsw9g-phy-gmii-sel
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2023-10-24 12:59:35 +02:00
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- ti,j784s4-cpsw9g-phy-gmii-sel
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2023-08-30 17:31:07 +02:00
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then:
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properties:
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ti,qsgmii-main-ports: false
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- if:
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properties:
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compatible:
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contains:
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enum:
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- ti,am3352-phy-gmii-sel
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- ti,am43xx-phy-gmii-sel
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then:
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properties:
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'#phy-cells':
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const: 2
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description: |
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- CPSW port number (starting from 1)
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- RMII refclk mode
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required:
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- compatible
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- reg
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- '#phy-cells'
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additionalProperties: false
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examples:
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- |
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phy_gmii_sel: phy@650 {
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compatible = "ti,am3352-phy-gmii-sel";
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reg = <0x650 0x4>;
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#phy-cells = <2>;
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};
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