128 lines
3.7 KiB
YAML
128 lines
3.7 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5018-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm IPQ5018 TLMM pin controller
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maintainers:
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- Bjorn Andersson <andersson@kernel.org>
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- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm IPQ5018 SoC.
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properties:
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compatible:
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const: qcom,ipq5018-tlmm
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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interrupt-controller: true
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"#interrupt-cells": true
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gpio-controller: true
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"#gpio-cells": true
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gpio-ranges: true
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wakeup-parent: true
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 24
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gpio-line-names:
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maxItems: 47
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-ipq5018-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-ipq5018-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-ipq5018-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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pattern: "^gpio([0-9]|[1-3][0-9]|4[0-6])$"
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minItems: 1
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maxItems: 8
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ atest_char, audio_pdm0, audio_pdm1, audio_rxbclk, audio_rxd,
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audio_rxfsync, audio_rxmclk, audio_txbclk, audio_txd,
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audio_txfsync, audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart0,
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blsp0_uart1, blsp1_i2c0, blsp1_i2c1, blsp1_spi0, blsp1_spi1,
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blsp1_uart0, blsp1_uart1, blsp1_uart2, blsp2_i2c0, blsp2_i2c1,
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blsp2_spi, blsp2_spi0, blsp2_spi1, btss, burn0, burn1, cri_trng,
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cri_trng0, cri_trng1, cxc_clk, cxc_data, dbg_out, eud_gpio,
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gcc_plltest, gcc_tlmm, gpio, led0, led2, mac0, mac1, mdc, mdio,
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pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake, pll_test,
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prng_rosc, pwm0, pwm1, pwm2, pwm3, qdss_cti_trig_in_a0,
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qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, qdss_cti_trig_in_b1,
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qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
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qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
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qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
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qdss_tracedata_a, qdss_tracedata_b, qspi_clk, qspi_cs,
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qspi_data, reset_out, sdc1_clk, sdc1_cmd, sdc1_data, wci_txd,
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wci_rxd, wsa_swrm, wsi_clk3, wsi_data3, wsis_reset, xfem ]
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required:
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- pins
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq5018-tlmm";
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reg = <0x01000000 0x300000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm 0 0 47>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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uart-w-state {
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rx-pins {
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pins = "gpio33";
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function = "blsp1_uart1";
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bias-pull-down;
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};
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tx-pins {
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pins = "gpio34";
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function = "blsp1_uart1";
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bias-pull-down;
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};
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};
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};
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...
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