2023-08-30 17:31:07 +02:00
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,sa8775p-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. SA8775P TLMM block
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maintainers:
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- Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
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description: |
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Top Level Mode Multiplexer pin controller in Qualcomm SA8775P SoC.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,sa8775p-tlmm
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reg:
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maxItems: 1
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interrupts: true
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interrupt-controller: true
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"#interrupt-cells": true
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gpio-controller: true
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"#gpio-cells": true
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gpio-ranges: true
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 74
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gpio-line-names:
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maxItems: 148
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required:
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- compatible
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- reg
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additionalProperties: false
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-sa8775p-tlmm-state"
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- patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-sa8775p-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-sa8775p-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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2023-10-24 12:59:35 +02:00
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unevaluatedProperties: false
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2023-08-30 17:31:07 +02:00
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[0-7])$"
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- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, ufs_reset ]
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minItems: 1
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maxItems: 16
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ atest_char, atest_usb2, audio_ref, cam_mclk, cci_async, cci_i2c,
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cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
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cci_timer5, cci_timer6, cci_timer7, cci_timer8, cci_timer9,
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cri_trng, cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0,
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ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4, ddr_pxi5, edp0_hot,
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edp0_lcd, edp1_hot, edp1_lcd, edp2_hot, edp2_lcd, edp3_hot,
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edp3_lcd, emac0_mcg0, emac0_mcg1, emac0_mcg2, emac0_mcg3,
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emac0_mdc, emac0_mdio, emac0_ptp_aux, emac0_ptp_pps, emac1_mcg0,
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emac1_mcg1, emac1_mcg2, emac1_mcg3, emac1_mdc, emac1_mdio,
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emac1_ptp_aux, emac1_ptp_pps, gcc_gp1, gcc_gp2, gcc_gp3,
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2023-10-24 12:59:35 +02:00
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gcc_gp4, gcc_gp5, gpio, hs0_mi2s, hs1_mi2s, hs2_mi2s, ibi_i3c,
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2023-08-30 17:31:07 +02:00
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jitter_bist, mdp0_vsync0, mdp0_vsync1, mdp0_vsync2, mdp0_vsync3,
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mdp0_vsync4, mdp0_vsync5, mdp0_vsync6, mdp0_vsync7, mdp0_vsync8,
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mdp1_vsync0, mdp1_vsync1, mdp1_vsync2, mdp1_vsync3, mdp1_vsync4,
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mdp1_vsync5, mdp1_vsync6, mdp1_vsync7, mdp1_vsync8, mdp_vsync,
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mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws, mi2s2_data0,
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mi2s2_data1, mi2s2_sck, mi2s2_ws, mi2s_mclk0, mi2s_mclk1,
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pcie0_clkreq, pcie1_clkreq, phase_flag, pll_bist, pll_clk,
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prng_rosc0, prng_rosc1, prng_rosc2, prng_rosc3, qdss_cti,
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qdss_gpio, qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4,
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qup0_se5, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4,
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qup1_se5, qup1_se6, qup2_se0, qup2_se1, qup2_se2, qup2_se3,
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qup2_se4, qup2_se5, qup2_se6, qup3_se0, sailss_emac0,
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sailss_ospi, sail_top, sgmii_phy, tb_trig, tgu_ch0, tgu_ch1,
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tgu_ch2, tgu_ch3, tgu_ch4, tgu_ch5, tsense_pwm1, tsense_pwm2,
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tsense_pwm3, tsense_pwm4, usb2phy_ac, vsense_trigger ]
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required:
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- pins
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@f000000 {
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compatible = "qcom,sa8775p-tlmm";
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reg = <0xf000000 0x1000000>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&tlmm 0 0 148>;
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qup-uart10-state {
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pins = "gpio46", "gpio47";
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function = "qup1_se3";
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};
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};
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...
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