199 lines
6.3 KiB
YAML
199 lines
6.3 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/remoteproc/ti,k3-dsp-rproc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: TI K3 DSP devices
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maintainers:
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- Suman Anna <s-anna@ti.com>
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description: |
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The TI K3 family of SoCs usually have one or more TI DSP Core sub-systems
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that are used to offload some of the processor-intensive tasks or algorithms,
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for achieving various system level goals.
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These processor sub-systems usually contain additional sub-modules like
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L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory
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controller, a dedicated local power/sleep controller etc. The DSP processor
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cores in the K3 SoCs are usually either a TMS320C66x CorePac processor or a
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TMS320C71x CorePac processor.
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Each DSP Core sub-system is represented as a single DT node. Each node has a
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number of required or optional properties that enable the OS running on the
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host processor (Arm CorePac) to perform the device management of the remote
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processor and to communicate with the remote processor.
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allOf:
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- $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
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properties:
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compatible:
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enum:
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- ti,am62a-c7xv-dsp
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- ti,j721e-c66-dsp
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- ti,j721e-c71-dsp
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- ti,j721s2-c71-dsp
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description:
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Use "ti,am62a-c7xv-dsp" for AM62A Deep learning DSPs on K3 AM62A SoCs
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Use "ti,j721e-c66-dsp" for C66x DSPs on K3 J721E SoCs
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Use "ti,j721e-c71-dsp" for C71x DSPs on K3 J721E SoCs
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Use "ti,j721s2-c71-dsp" for C71x DSPs on K3 J721S2 SoCs
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resets:
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description: |
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Should contain the phandle to the reset controller node managing the
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local resets for this device, and a reset specifier.
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maxItems: 1
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firmware-name:
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description: |
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Should contain the name of the default firmware image
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file located on the firmware search path
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mboxes:
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description: |
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OMAP Mailbox specifier denoting the sub-mailbox, to be used for
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communication with the remote processor. This property should match
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with the sub-mailbox node used in the firmware image.
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maxItems: 1
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memory-region:
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minItems: 2
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maxItems: 8
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description: |
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phandle to the reserved memory nodes to be associated with the remoteproc
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device. There should be at least two reserved memory nodes defined. The
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reserved memory nodes should be carveout nodes, and should be defined as
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per the bindings in
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Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
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items:
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- description: region used for dynamic DMA allocations like vrings and
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vring buffers
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- description: region reserved for firmware image sections
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additionalItems: true
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# Optional properties:
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# --------------------
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sram:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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minItems: 1
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maxItems: 4
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items:
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maxItems: 1
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description: |
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phandles to one or more reserved on-chip SRAM regions. The regions
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should be defined as child nodes of the respective SRAM node, and
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should be defined as per the generic bindings in,
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Documentation/devicetree/bindings/sram/sram.yaml
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if:
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properties:
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compatible:
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enum:
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- ti,j721e-c66-dsp
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then:
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properties:
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reg:
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items:
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- description: Address and Size of the L2 SRAM internal memory region
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- description: Address and Size of the L1 PRAM internal memory region
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- description: Address and Size of the L1 DRAM internal memory region
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reg-names:
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items:
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- const: l2sram
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- const: l1pram
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- const: l1dram
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else:
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if:
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properties:
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compatible:
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enum:
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- ti,am62a-c7xv-dsp
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- ti,j721e-c71-dsp
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- ti,j721s2-c71-dsp
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then:
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properties:
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reg:
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items:
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- description: Address and Size of the L2 SRAM internal memory region
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- description: Address and Size of the L1 DRAM internal memory region
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reg-names:
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items:
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- const: l2sram
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- const: l1dram
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required:
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- compatible
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- reg
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- reg-names
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- ti,sci
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- ti,sci-dev-id
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- ti,sci-proc-ids
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- resets
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- firmware-name
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- mboxes
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- memory-region
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unevaluatedProperties: false
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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mailbox0_cluster3: mailbox-0 {
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#mbox-cells = <1>;
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};
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mailbox0_cluster4: mailbox-1 {
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#mbox-cells = <1>;
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};
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bus@100000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
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<0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71_0 */
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<0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
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<0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>; /* C66_1 */
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/* J721E C66_0 DSP node */
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dsp@4d80800000 {
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compatible = "ti,j721e-c66-dsp";
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reg = <0x4d 0x80800000 0x00 0x00048000>,
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<0x4d 0x80e00000 0x00 0x00008000>,
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<0x4d 0x80f00000 0x00 0x00008000>;
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reg-names = "l2sram", "l1pram", "l1dram";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <142>;
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ti,sci-proc-ids = <0x03 0xFF>;
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resets = <&k3_reset 142 1>;
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firmware-name = "j7-c66_0-fw";
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memory-region = <&c66_0_dma_memory_region>,
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<&c66_0_memory_region>;
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mboxes = <&mailbox0_cluster3 &mbox_c66_0>;
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};
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/* J721E C71_0 DSP node */
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c71_0: dsp@64800000 {
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compatible = "ti,j721e-c71-dsp";
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reg = <0x00 0x64800000 0x00 0x00080000>,
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<0x00 0x64e00000 0x00 0x0000c000>;
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reg-names = "l2sram", "l1dram";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <15>;
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ti,sci-proc-ids = <0x30 0xFF>;
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resets = <&k3_reset 15 1>;
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firmware-name = "j7-c71_0-fw";
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memory-region = <&c71_0_dma_memory_region>,
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<&c71_0_memory_region>;
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mboxes = <&mailbox0_cluster4 &mbox_c71_0>;
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};
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};
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};
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