136 lines
4.5 KiB
YAML
136 lines
4.5 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/remoteproc/xlnx,zynqmp-r5fss.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx R5F processor subsystem
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maintainers:
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- Ben Levinsky <ben.levinsky@amd.com>
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- Tanmay Shah <tanmay.shah@amd.com>
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description: |
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The Xilinx platforms include a pair of Cortex-R5F processors (RPU) for
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real-time processing based on the Cortex-R5F processor core from ARM.
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The Cortex-R5F processor implements the Arm v7-R architecture and includes a
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floating-point unit that implements the Arm VFPv3 instruction set.
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properties:
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compatible:
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const: xlnx,zynqmp-r5fss
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xlnx,cluster-mode:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2]
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description: |
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The RPU MPCore can operate in split mode (Dual-processor performance), Safety
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lock-step mode(Both RPU cores execute the same code in lock-step,
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clock-for-clock) or Single CPU mode (RPU core 0 is held in reset while
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core 1 runs normally). The processor does not support dynamic configuration.
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Switching between modes is only permitted immediately after a processor reset.
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If set to 1 then lockstep mode and if 0 then split mode.
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If set to 2 then single CPU mode. When not defined, default will be lockstep mode.
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In summary,
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0: split mode
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1: lockstep mode (default)
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2: single cpu mode
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patternProperties:
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"^r5f-[a-f0-9]+$":
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type: object
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description: |
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The RPU is located in the Low Power Domain of the Processor Subsystem.
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Each processor includes separate L1 instruction and data caches and
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tightly coupled memories (TCM). System memory is cacheable, but the TCM
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memory space is non-cacheable.
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Each RPU contains one 64KB memory and two 32KB memories that
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are accessed via the TCM A and B port interfaces, for a total of 128KB
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per processor. In lock-step mode, the processor has access to 256KB of
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TCM memory.
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properties:
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compatible:
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const: xlnx,zynqmp-r5f
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power-domains:
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maxItems: 1
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mboxes:
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minItems: 1
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items:
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- description: mailbox channel to send data to RPU
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- description: mailbox channel to receive data from RPU
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mbox-names:
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minItems: 1
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items:
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- const: tx
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- const: rx
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sram:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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minItems: 1
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maxItems: 8
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items:
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maxItems: 1
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description: |
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phandles to one or more reserved on-chip SRAM regions. Other than TCM,
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the RPU can execute instructions and access data from the OCM memory,
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the main DDR memory, and other system memories.
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The regions should be defined as child nodes of the respective SRAM
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node, and should be defined as per the generic bindings in
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Documentation/devicetree/bindings/sram/sram.yaml
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memory-region:
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description: |
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List of phandles to the reserved memory regions associated with the
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remoteproc device. This is variable and describes the memories shared with
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the remote processor (e.g. remoteproc firmware and carveouts, rpmsg
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vrings, ...). This reserved memory region will be allocated in DDR memory.
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minItems: 1
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maxItems: 8
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items:
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- description: region used for RPU firmware image section
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- description: vdev buffer
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- description: vring0
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- description: vring1
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additionalItems: true
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required:
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- compatible
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- power-domains
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unevaluatedProperties: false
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required:
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- compatible
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additionalProperties: false
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examples:
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- |
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remoteproc {
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compatible = "xlnx,zynqmp-r5fss";
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xlnx,cluster-mode = <1>;
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r5f-0 {
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compatible = "xlnx,zynqmp-r5f";
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power-domains = <&zynqmp_firmware 0x7>;
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memory-region = <&rproc_0_fw_image>, <&rpu0vdev0buffer>, <&rpu0vdev0vring0>, <&rpu0vdev0vring1>;
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mboxes = <&ipi_mailbox_rpu0 0>, <&ipi_mailbox_rpu0 1>;
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mbox-names = "tx", "rx";
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};
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r5f-1 {
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compatible = "xlnx,zynqmp-r5f";
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power-domains = <&zynqmp_firmware 0x8>;
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memory-region = <&rproc_1_fw_image>, <&rpu1vdev0buffer>, <&rpu1vdev0vring0>, <&rpu1vdev0vring1>;
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mboxes = <&ipi_mailbox_rpu1 0>, <&ipi_mailbox_rpu1 1>;
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mbox-names = "tx", "rx";
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};
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};
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...
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