251 lines
9.5 KiB
YAML
251 lines
9.5 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0 OR MIT)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/riscv/extensions.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: RISC-V ISA extensions
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maintainers:
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- Paul Walmsley <paul.walmsley@sifive.com>
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- Palmer Dabbelt <palmer@sifive.com>
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- Conor Dooley <conor@kernel.org>
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description: |
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RISC-V has a large number of extensions, some of which are "standard"
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extensions, meaning they are ratified by RISC-V International, and others
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are "vendor" extensions.
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This document defines properties that indicate whether a hart supports a
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given extension.
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Once a standard extension has been ratified, no changes in behaviour can be
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made without the creation of a new extension.
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The properties for standard extensions therefore map to their originally
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ratified states, with the exception of the I, Zicntr & Zihpm extensions.
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See the "i" property for more information.
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select:
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properties:
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compatible:
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contains:
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const: riscv
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properties:
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riscv,isa:
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description:
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Identifies the specific RISC-V instruction set architecture
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supported by the hart. These are documented in the RISC-V
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User-Level ISA document, available from
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https://riscv.org/specifications/
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Due to revisions of the ISA specification, some deviations
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have arisen over time.
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Notably, riscv,isa was defined prior to the creation of the
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Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i"
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implies "zicntr_zicsr_zifencei_zihpm".
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While the isa strings in ISA specification are case
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insensitive, letters in the riscv,isa string must be all
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lowercase.
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$ref: /schemas/types.yaml#/definitions/string
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pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$
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deprecated: true
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riscv,isa-base:
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description:
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The base ISA implemented by this hart, as described by the 20191213
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version of the unprivileged ISA specification.
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enum:
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- rv32i
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- rv64i
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riscv,isa-extensions:
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$ref: /schemas/types.yaml#/definitions/string-array
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minItems: 1
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description: Extensions supported by the hart.
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items:
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anyOf:
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# single letter extensions, in canonical order
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- const: i
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description: |
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The base integer instruction set, as ratified in the 20191213
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version of the unprivileged ISA specification.
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This does not include Chapter 10, "Counters", which was moved into
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the Zicntr and Zihpm extensions after the ratification of the
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20191213 version of the unprivileged specification.
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- const: m
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description:
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The standard M extension for integer multiplication and division, as
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ratified in the 20191213 version of the unprivileged ISA
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specification.
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- const: a
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description:
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The standard A extension for atomic instructions, as ratified in the
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20191213 version of the unprivileged ISA specification.
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- const: f
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description:
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The standard F extension for single-precision floating point, as
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ratified in the 20191213 version of the unprivileged ISA
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specification.
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- const: d
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description:
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The standard D extension for double-precision floating-point, as
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ratified in the 20191213 version of the unprivileged ISA
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specification.
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- const: q
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description:
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The standard Q extension for quad-precision floating-point, as
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ratified in the 20191213 version of the unprivileged ISA
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specification.
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- const: c
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description:
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The standard C extension for compressed instructions, as ratified in
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the 20191213 version of the unprivileged ISA specification.
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- const: v
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description:
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The standard V extension for vector operations, as ratified
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in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f
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encoding") of the riscv-v-spec.
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- const: h
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description:
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The standard H extension for hypervisors as ratified in the 20191213
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version of the privileged ISA specification.
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# multi-letter extensions, sorted alphanumerically
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- const: smaia
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description: |
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The standard Smaia supervisor-level extension for the advanced
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interrupt architecture for machine-mode-visible csr and behavioural
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changes to interrupts as frozen at commit ccbddab ("Merge pull
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request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
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- const: ssaia
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description: |
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The standard Ssaia supervisor-level extension for the advanced
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interrupt architecture for supervisor-mode-visible csr and
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behavioural changes to interrupts as frozen at commit ccbddab
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("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
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- const: sscofpmf
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description: |
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The standard Sscofpmf supervisor-level extension for count overflow
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and mode-based filtering as ratified at commit 01d1df0 ("Add ability
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to manually trigger workflow. (#2)") of riscv-count-overflow.
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- const: sstc
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description: |
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The standard Sstc supervisor-level extension for time compare as
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ratified at commit 3f9ed34 ("Add ability to manually trigger
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workflow. (#2)") of riscv-time-compare.
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- const: svinval
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description:
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The standard Svinval supervisor-level extension for fine-grained
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address-translation cache invalidation as ratified in the 20191213
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version of the privileged ISA specification.
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- const: svnapot
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description:
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The standard Svnapot supervisor-level extensions for napot
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translation contiguity as ratified in the 20191213 version of the
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privileged ISA specification.
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- const: svpbmt
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description:
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The standard Svpbmt supervisor-level extensions for page-based
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memory types as ratified in the 20191213 version of the privileged
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ISA specification.
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- const: zba
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description: |
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The standard Zba bit-manipulation extension for address generation
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acceleration instructions as ratified at commit 6d33919 ("Merge pull
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request #158 from hirooih/clmul-fix-loop-end-condition") of
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riscv-bitmanip.
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- const: zbb
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description: |
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The standard Zbb bit-manipulation extension for basic bit-manipulation
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as ratified at commit 6d33919 ("Merge pull request #158 from
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hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
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- const: zbc
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description: |
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The standard Zbc bit-manipulation extension for carry-less
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multiplication as ratified at commit 6d33919 ("Merge pull request
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#158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
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- const: zbs
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description: |
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The standard Zbs bit-manipulation extension for single-bit
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instructions as ratified at commit 6d33919 ("Merge pull request #158
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from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
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- const: zicbom
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description:
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The standard Zicbom extension for base cache management operations as
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ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
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- const: zicbop
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description:
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The standard Zicbop extension for cache-block prefetch instructions
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as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of
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riscv-CMOs.
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- const: zicboz
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description:
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The standard Zicboz extension for cache-block zeroing as ratified
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in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
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- const: zicntr
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description:
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The standard Zicntr extension for base counters and timers, as
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ratified in the 20191213 version of the unprivileged ISA
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specification.
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- const: zicsr
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description: |
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The standard Zicsr extension for control and status register
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instructions, as ratified in the 20191213 version of the
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unprivileged ISA specification.
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This does not include Chapter 10, "Counters", which documents
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special case read-only CSRs, that were moved into the Zicntr and
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Zihpm extensions after the ratification of the 20191213 version of
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the unprivileged specification.
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- const: zifencei
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description:
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The standard Zifencei extension for instruction-fetch fence, as
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ratified in the 20191213 version of the unprivileged ISA
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specification.
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- const: zihintpause
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description:
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The standard Zihintpause extension for pause hints, as ratified in
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commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.
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- const: zihpm
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description:
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The standard Zihpm extension for hardware performance counters, as
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ratified in the 20191213 version of the unprivileged ISA
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specification.
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- const: ztso
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description:
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The standard Ztso extension for total store ordering, as ratified
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in commit 2e5236 ("Ztso is now ratified.") of the
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riscv-isa-manual.
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additionalProperties: true
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...
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