2023-08-30 17:31:07 +02:00
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/rtc/xlnx,zynqmp-rtc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
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description:
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RTC controller for the Xilinx Zynq MPSoC Real Time Clock.
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The RTC controller has separate IRQ lines for seconds and alarm.
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maintainers:
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2023-10-24 12:59:35 +02:00
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- Michal Simek <michal.simek@amd.com>
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2023-08-30 17:31:07 +02:00
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allOf:
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- $ref: rtc.yaml#
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properties:
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compatible:
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const: xlnx,zynqmp-rtc
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: rtc
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interrupts:
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maxItems: 2
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interrupt-names:
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items:
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- const: alarm
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- const: sec
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calibration:
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description: |
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calibration value for 1 sec period which will
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be programmed directly to calibration register.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0x1
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maximum: 0x1FFFFF
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default: 0x198233
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deprecated: true
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-names
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additionalProperties: false
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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rtc: rtc@ffa60000 {
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compatible = "xlnx,zynqmp-rtc";
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reg = <0x0 0xffa60000 0x0 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <0 26 4>, <0 27 4>;
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interrupt-names = "alarm", "sec";
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calibration = <0x198233>;
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clock-names = "rtc";
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clocks = <&rtc_clk>;
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};
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};
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