2023-08-30 17:31:07 +02:00
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-disp-blk-ctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX8MM DISP blk-ctrl
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maintainers:
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- Lucas Stach <l.stach@pengutronix.de>
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description:
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The i.MX8MM DISP blk-ctrl is a top-level peripheral providing access to
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the NoC and ensuring proper power sequencing of the display and MIPI CSI
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peripherals located in the DISP domain of the SoC.
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properties:
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compatible:
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items:
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- const: fsl,imx8mm-disp-blk-ctrl
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- const: syscon
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reg:
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maxItems: 1
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'#power-domain-cells':
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const: 1
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power-domains:
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minItems: 5
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maxItems: 5
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power-domain-names:
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items:
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- const: bus
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- const: csi-bridge
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- const: lcdif
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- const: mipi-dsi
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- const: mipi-csi
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clocks:
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minItems: 10
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maxItems: 10
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clock-names:
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items:
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- const: csi-bridge-axi
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- const: csi-bridge-apb
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- const: csi-bridge-core
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- const: lcdif-axi
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- const: lcdif-apb
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- const: lcdif-pix
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- const: dsi-pclk
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- const: dsi-ref
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- const: csi-aclk
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- const: csi-pclk
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required:
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- compatible
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- reg
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- power-domains
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- power-domain-names
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8mm-clock.h>
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#include <dt-bindings/power/imx8mm-power.h>
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2023-10-24 12:59:35 +02:00
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blk-ctrl@32e28000 {
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2023-08-30 17:31:07 +02:00
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compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
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reg = <0x32e28000 0x100>;
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power-domains = <&pgc_dispmix>, <&pgc_dispmix>, <&pgc_dispmix>,
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<&pgc_mipi>, <&pgc_mipi>;
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power-domain-names = "bus", "csi-bridge", "lcdif",
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"mipi-dsi", "mipi-csi";
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clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
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<&clk IMX8MM_CLK_DISP_APB_ROOT>,
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<&clk IMX8MM_CLK_CSI1_ROOT>,
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<&clk IMX8MM_CLK_DISP_AXI_ROOT>,
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<&clk IMX8MM_CLK_DISP_APB_ROOT>,
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<&clk IMX8MM_CLK_DISP_ROOT>,
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<&clk IMX8MM_CLK_DSI_CORE>,
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<&clk IMX8MM_CLK_DSI_PHY_REF>,
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<&clk IMX8MM_CLK_CSI1_CORE>,
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<&clk IMX8MM_CLK_CSI1_PHY_REF>;
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clock-names = "csi-bridge-axi", "csi-bridge-apb", "csi-bridge-core",
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"lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk",
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"dsi-ref", "csi-aclk", "csi-pclk";
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#power-domain-cells = <1>;
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};
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