69 lines
2.3 KiB
Plaintext
69 lines
2.3 KiB
Plaintext
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Freescale Enhanced Serial Audio Interface (ESAI) Controller
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The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port
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for serial communication with a variety of serial devices, including industry
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standard codecs, Sony/Phillips Digital Interface (S/PDIF) transceivers, and
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other DSPs. It has up to six transmitters and four receivers.
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Required properties:
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- compatible : Compatible list, should contain one of the following
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compatibles:
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"fsl,imx35-esai",
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"fsl,vf610-esai",
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"fsl,imx6ull-esai",
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"fsl,imx8qm-esai",
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- reg : Offset and length of the register set for the device.
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- interrupts : Contains the spdif interrupt.
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- dmas : Generic dma devicetree binding as described in
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Documentation/devicetree/bindings/dma/dma.txt.
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- dma-names : Two dmas have to be defined, "tx" and "rx".
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- clocks : Contains an entry for each entry in clock-names.
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- clock-names : Includes the following entries:
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"core" The core clock used to access registers
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"extal" The esai baud clock for esai controller used to
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derive HCK, SCK and FS.
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"fsys" The system clock derived from ahb clock used to
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derive HCK, SCK and FS.
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"spba" The spba clock is required when ESAI is placed as a
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bus slave of the Shared Peripheral Bus and when two
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or more bus masters (CPU, DMA or DSP) try to access
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it. This property is optional depending on the SoC
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design.
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- fsl,fifo-depth : The number of elements in the transmit and receive
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FIFOs. This number is the maximum allowed value for
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TFCR[TFWM] or RFCR[RFWM].
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- fsl,esai-synchronous: This is a boolean property. If present, indicating
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that ESAI would work in the synchronous mode, which
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means all the settings for Receiving would be
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duplicated from Transmition related registers.
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Optional properties:
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- big-endian : If this property is absent, the native endian mode
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will be in use as default, or the big endian mode
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will be in use for all the device registers.
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Example:
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esai: esai@2024000 {
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compatible = "fsl,imx35-esai";
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reg = <0x02024000 0x4000>;
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interrupts = <0 51 0x04>;
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clocks = <&clks 208>, <&clks 118>, <&clks 208>;
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clock-names = "core", "extal", "fsys";
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dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
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dma-names = "rx", "tx";
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fsl,fifo-depth = <128>;
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fsl,esai-synchronous;
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big-endian;
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};
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