2023-08-30 17:31:07 +02:00
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/sound/mt8195-afe-pcm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek AFE PCM controller for mt8195
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maintainers:
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- Trevor Wu <trevor.wu@mediatek.com>
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properties:
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compatible:
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const: mediatek,mt8195-audio
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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resets:
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maxItems: 1
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reset-names:
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const: audiosys
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memory-region:
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maxItems: 1
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description: |
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Shared memory region for AFE memif. A "shared-dma-pool".
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See ../reserved-memory/reserved-memory.txt for details.
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mediatek,topckgen:
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2023-10-24 12:59:35 +02:00
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$ref: /schemas/types.yaml#/definitions/phandle
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2023-08-30 17:31:07 +02:00
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description: The phandle of the mediatek topckgen controller
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power-domains:
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maxItems: 1
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clocks:
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items:
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- description: 26M clock
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- description: audio pll1 clock
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- description: audio pll2 clock
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- description: clock divider for i2si1_mck
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- description: clock divider for i2si2_mck
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- description: clock divider for i2so1_mck
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- description: clock divider for i2so2_mck
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- description: clock divider for dptx_mck
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- description: a1sys hoping clock
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- description: audio intbus clock
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- description: audio hires clock
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- description: audio local bus clock
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- description: mux for dptx_mck
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- description: mux for i2so1_mck
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- description: mux for i2so2_mck
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- description: mux for i2si1_mck
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- description: mux for i2si2_mck
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- description: audio infra 26M clock
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- description: infra bus clock
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clock-names:
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items:
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- const: clk26m
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- const: apll1_ck
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- const: apll2_ck
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- const: apll12_div0
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- const: apll12_div1
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- const: apll12_div2
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- const: apll12_div3
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- const: apll12_div9
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- const: a1sys_hp_sel
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- const: aud_intbus_sel
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- const: audio_h_sel
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- const: audio_local_bus_sel
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- const: dptx_m_sel
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- const: i2so1_m_sel
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- const: i2so2_m_sel
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- const: i2si1_m_sel
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- const: i2si2_m_sel
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- const: infra_ao_audio_26m_b
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- const: scp_adsp_audiodsp
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mediatek,etdm-in1-chn-disabled:
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$ref: /schemas/types.yaml#/definitions/uint8-array
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maxItems: 24
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description: Specify which input channel should be disabled.
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mediatek,etdm-in2-chn-disabled:
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$ref: /schemas/types.yaml#/definitions/uint8-array
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maxItems: 16
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description: Specify which input channel should be disabled.
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patternProperties:
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"^mediatek,etdm-in[1-2]-mclk-always-on-rate-hz$":
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description: Specify etdm in mclk output rate for always on case.
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"^mediatek,etdm-out[1-3]-mclk-always-on-rate-hz$":
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description: Specify etdm out mclk output rate for always on case.
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"^mediatek,etdm-in[1-2]-multi-pin-mode$":
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type: boolean
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description: if present, the etdm data mode is I2S.
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"^mediatek,etdm-out[1-3]-multi-pin-mode$":
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type: boolean
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description: if present, the etdm data mode is I2S.
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"^mediatek,etdm-in[1-2]-cowork-source$":
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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etdm modules can share the same external clock pin. Specify
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which etdm clock source is required by this etdm in moudule.
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enum:
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- 0 # etdm1_in
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- 1 # etdm2_in
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- 2 # etdm1_out
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- 3 # etdm2_out
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"^mediatek,etdm-out[1-2]-cowork-source$":
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$ref: /schemas/types.yaml#/definitions/uint32
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description: |
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etdm modules can share the same external clock pin. Specify
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which etdm clock source is required by this etdm out moudule.
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enum:
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- 0 # etdm1_in
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- 1 # etdm2_in
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- 2 # etdm1_out
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- 3 # etdm2_out
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required:
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- compatible
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- reg
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- interrupts
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- resets
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- reset-names
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- mediatek,topckgen
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- power-domains
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- clocks
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- clock-names
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- memory-region
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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afe: mt8195-afe-pcm@10890000 {
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compatible = "mediatek,mt8195-audio";
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reg = <0x10890000 0x10000>;
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interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
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resets = <&watchdog 14>;
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reset-names = "audiosys";
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mediatek,topckgen = <&topckgen>;
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power-domains = <&spm 7>; //MT8195_POWER_DOMAIN_AUDIO
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memory-region = <&snd_dma_mem_reserved>;
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clocks = <&clk26m>,
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<&topckgen 163>, //CLK_TOP_APLL1
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<&topckgen 166>, //CLK_TOP_APLL2
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<&topckgen 233>, //CLK_TOP_APLL12_DIV0
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<&topckgen 234>, //CLK_TOP_APLL12_DIV1
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<&topckgen 235>, //CLK_TOP_APLL12_DIV2
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<&topckgen 236>, //CLK_TOP_APLL12_DIV3
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<&topckgen 238>, //CLK_TOP_APLL12_DIV9
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<&topckgen 100>, //CLK_TOP_A1SYS_HP_SEL
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<&topckgen 33>, //CLK_TOP_AUD_INTBUS_SEL
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<&topckgen 34>, //CLK_TOP_AUDIO_H_SEL
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<&topckgen 107>, //CLK_TOP_AUDIO_LOCAL_BUS_SEL
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<&topckgen 98>, //CLK_TOP_DPTX_M_SEL
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<&topckgen 94>, //CLK_TOP_I2SO1_M_SEL
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<&topckgen 95>, //CLK_TOP_I2SO2_M_SEL
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<&topckgen 96>, //CLK_TOP_I2SI1_M_SEL
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<&topckgen 97>, //CLK_TOP_I2SI2_M_SEL
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<&infracfg_ao 50>, //CLK_INFRA_AO_AUDIO_26M_B
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<&scp_adsp 0>; //CLK_SCP_ADSP_AUDIODSP
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clock-names = "clk26m",
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"apll1_ck",
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"apll2_ck",
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"apll12_div0",
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"apll12_div1",
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"apll12_div2",
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"apll12_div3",
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"apll12_div9",
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"a1sys_hp_sel",
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"aud_intbus_sel",
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"audio_h_sel",
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"audio_local_bus_sel",
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"dptx_m_sel",
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"i2so1_m_sel",
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"i2so2_m_sel",
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"i2si1_m_sel",
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"i2si2_m_sel",
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"infra_ao_audio_26m_b",
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"scp_adsp_audiodsp";
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};
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...
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