89 lines
2.2 KiB
YAML
89 lines
2.2 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/sound/wlf,wm8960.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Wolfson WM8960 audio codec
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maintainers:
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- patches@opensource.cirrus.com
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properties:
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compatible:
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const: wlf,wm8960
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: mclk
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'#sound-dai-cells':
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const: 0
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wlf,capless:
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type: boolean
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description:
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If present, OUT3 pin will be enabled and disabled together with HP_L and
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HP_R pins in response to jack detect events.
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wlf,gpio-cfg:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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maxItems: 2
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description: |
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A list of GPIO configuration register values.
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- gpio-cfg[0]: ALRCGPIO of R9 (Audio interface)
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- gpio-cfg[1]: {GPIOPOL:GPIOSEL[2:0]} of R48 (Additional Control 4).
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wlf,hp-cfg:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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maxItems: 3
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description: |
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A list of headphone jack detect configuration register values:
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- hp-cfg[0]: HPSEL[1:0] of R48 (Additional Control 4).
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- hp-cfg[1]: {HPSWEN:HPSWPOL} of R24 (Additional Control 2).
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- hp-cfg[2]: {TOCLKSEL:TOEN} of R23 (Additional Control 1).
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wlf,shared-lrclk:
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type: boolean
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description:
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If present, the LRCM bit of R24 (Additional control 2) gets set,
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indicating that ADCLRC and DACLRC pins will be disabled only when ADC
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(Left and Right) and DAC (Left and Right) are disabled.
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When WM8960 works on synchronize mode and DACLRC pin is used to supply
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frame clock, it will no frame clock for captrue unless enable DAC to
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enable DACLRC pin. If shared-lrclk is present, no need to enable DAC for
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captrue.
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required:
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- compatible
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- reg
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allOf:
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- $ref: dai-common.yaml#
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unevaluatedProperties: false
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examples:
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- |
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i2c {
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#address-cells = <1>;
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#size-cells = <0>;
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audio-codec@1a {
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compatible = "wlf,wm8960";
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reg = <0x1a>;
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clocks = <&clks 0>;
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clock-names = "mclk";
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#sound-dai-cells = <0>;
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wlf,hp-cfg = <3 2 3>;
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wlf,gpio-cfg = <1 3>;
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wlf,shared-lrclk;
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};
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};
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