104 lines
3.5 KiB
YAML
104 lines
3.5 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/sprd,spi-adi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Spreadtrum ADI controller
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maintainers:
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- Orson Zhai <orsonzhai@gmail.com>
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- Baolin Wang <baolin.wang7@gmail.com>
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- Chunyan Zhang <zhang.lyra@gmail.com>
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description: |
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ADI is the abbreviation of Anolog-Digital interface, which is used to access
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analog chip (such as PMIC) from digital chip. ADI controller follows the SPI
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framework for its hardware implementation is alike to SPI bus and its timing
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is compatile to SPI timing.
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ADI controller has 50 channels including 2 software read/write channels and
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48 hardware channels to access analog chip. For 2 software read/write channels,
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users should set ADI registers to access analog chip. For hardware channels,
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we can configure them to allow other hardware components to use it independently,
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which means we can just link one analog chip address to one hardware channel,
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then users can access the mapped analog chip address by this hardware channel
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triggered by hardware components instead of ADI software channels.
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Thus we introduce one property named "sprd,hw-channels" to configure hardware
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channels, the first value specifies the hardware channel id which is used to
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transfer data triggered by hardware automatically, and the second value specifies
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the analog chip address where user want to access by hardware components.
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Since we have multi-subsystems will use unique ADI to access analog chip, when
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one system is reading/writing data by ADI software channels, that should be under
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one hardware spinlock protection to prevent other systems from reading/writing
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data by ADI software channels at the same time, or two parallel routine of setting
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ADI registers will make ADI controller registers chaos to lead incorrect results.
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Then we need one hardware spinlock to synchronize between the multiple subsystems.
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The new version ADI controller supplies multiple master channels for different
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subsystem accessing, that means no need to add hardware spinlock to synchronize,
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thus change the hardware spinlock support to be optional to keep backward
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compatibility.
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allOf:
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- $ref: /schemas/spi/spi-controller.yaml#
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properties:
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compatible:
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enum:
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- sprd,sc9860-adi
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- sprd,sc9863-adi
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- sprd,ums512-adi
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reg:
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maxItems: 1
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hwlocks:
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maxItems: 1
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hwlock-names:
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const: adi
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sprd,hw-channels:
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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description: A list of hardware channels
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minItems: 1
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maxItems: 48
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items:
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items:
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- description: The hardware channel id which is used to transfer data
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triggered by hardware automatically, channel id 0-1 are for software
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use, 2-49 are hardware channels.
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minimum: 2
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maximum: 49
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- description: The analog chip address where user want to access by
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hardware components.
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required:
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- compatible
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- reg
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- '#address-cells'
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- '#size-cells'
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unevaluatedProperties: false
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examples:
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- |
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aon {
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#address-cells = <2>;
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#size-cells = <2>;
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adi_bus: spi@40030000 {
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compatible = "sprd,sc9860-adi";
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reg = <0 0x40030000 0 0x10000>;
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hwlocks = <&hwlock1 0>;
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hwlock-names = "adi";
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#address-cells = <1>;
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#size-cells = <0>;
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sprd,hw-channels = <30 0x8c20>;
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};
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};
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...
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