303 lines
12 KiB
YAML
303 lines
12 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/timer/renesas,rz-mtu3.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a)
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maintainers:
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- Biju Das <biju.das.jz@bp.renesas.com>
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description: |
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This hardware block consists of eight 16-bit timer channels and one
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32- bit timer channel. It supports the following specifications:
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- Pulse input/output: 28 lines max.
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- Pulse input 3 lines
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- Count clock 11 clocks for each channel (14 clocks for MTU0, 12 clocks
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for MTU2, and 10 clocks for MTU5, four clocks for MTU1-MTU2 combination
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(when LWA = 1))
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- Operating frequency Up to 100 MHz
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- Available operations [MTU0 to MTU4, MTU6, MTU7, and MTU8]
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- Waveform output on compare match
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- Input capture function (noise filter setting available)
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- Counter-clearing operation
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- Simultaneous writing to multiple timer counters (TCNT)
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(excluding MTU8).
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- Simultaneous clearing on compare match or input capture
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(excluding MTU8).
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- Simultaneous input and output to registers in synchronization with
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counter operations (excluding MTU8).
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- Up to 12-phase PWM output in combination with synchronous operation
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(excluding MTU8)
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- [MTU0 MTU3, MTU4, MTU6, MTU7, and MTU8]
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- Buffer operation specifiable
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- [MTU1, MTU2]
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- Phase counting mode can be specified independently
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- 32-bit phase counting mode can be specified for interlocked operation
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of MTU1 and MTU2 (when TMDR3.LWA = 1)
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- Cascade connection operation available
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- [MTU3, MTU4, MTU6, and MTU7]
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- Through interlocked operation of MTU3/4 and MTU6/7, the positive and
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negative signals in six phases (12 phases in total) can be output in
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complementary PWM and reset-synchronized PWM operation.
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- In complementary PWM mode, values can be transferred from buffer
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registers to temporary registers at crests and troughs of the timer-
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counter values or when the buffer registers (TGRD registers in MTU4
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and MTU7) are written to.
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- Double-buffering selectable in complementary PWM mode.
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- [MTU3 and MTU4]
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- Through interlocking with MTU0, a mode for driving AC synchronous
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motors (brushless DC motors) by using complementary PWM output and
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reset-synchronized PWM output is settable and allows the selection
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of two types of waveform output (chopping or level).
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- [MTU5]
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- Capable of operation as a dead-time compensation counter.
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- [MTU0/MTU5, MTU1, MTU2, and MTU8]
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- 32-bit phase counting mode specifiable by combining MTU1 and MTU2 and
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through interlocked operation with MTU0/MTU5 and MTU8.
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- Interrupt-skipping function
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- In complementary PWM mode, interrupts on crests and troughs of counter
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values and triggers to start conversion by the A/D converter can be
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skipped.
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- Interrupt sources: 43 sources.
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- Buffer operation:
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- Automatic transfer of register data (transfer from the buffer
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register to the timer register).
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- Trigger generation
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- A/D converter start triggers can be generated
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- A/D converter start request delaying function enables A/D converter
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to be started with any desired timing and to be synchronized with
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PWM output.
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- Low power consumption function
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- The MTU3a can be placed in the module-stop state.
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There are two phase counting modes. 16-bit phase counting mode in which
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MTU1 and MTU2 operate independently, and cascade connection 32-bit phase
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counting mode in which MTU1 and MTU2 are cascaded.
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In phase counting mode, the phase difference between two external input
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clocks is detected and the corresponding TCNT is incremented or
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decremented.
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The below counters are supported
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count0 - MTU1 16-bit phase counting
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count1 - MTU2 16-bit phase counting
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count2 - MTU1+ MTU2 32-bit phase counting
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The module supports PWM mode{1,2}, Reset-synchronized PWM mode and
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complementary PWM mode{1,2,3}.
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In complementary PWM mode, six positive-phase and six negative-phase PWM
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waveforms (12 phases in total) with dead time can be output by
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combining MTU{3,4} and MTU{6,7}.
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The below pwm channels are supported in pwm mode 1.
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pwm0 - MTU0.MTIOC0A PWM mode 1
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pwm1 - MTU0.MTIOC0C PWM mode 1
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pwm2 - MTU1.MTIOC1A PWM mode 1
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pwm3 - MTU2.MTIOC2A PWM mode 1
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pwm4 - MTU3.MTIOC3A PWM mode 1
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pwm5 - MTU3.MTIOC3C PWM mode 1
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pwm6 - MTU4.MTIOC4A PWM mode 1
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pwm7 - MTU4.MTIOC4C PWM mode 1
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pwm8 - MTU6.MTIOC6A PWM mode 1
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pwm9 - MTU6.MTIOC6C PWM mode 1
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pwm10 - MTU7.MTIOC7A PWM mode 1
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pwm11 - MTU7.MTIOC7C PWM mode 1
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properties:
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compatible:
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items:
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- enum:
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- renesas,r9a07g044-mtu3 # RZ/G2{L,LC}
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- renesas,r9a07g054-mtu3 # RZ/V2L
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- const: renesas,rz-mtu3
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reg:
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maxItems: 1
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interrupts:
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items:
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- description: MTU0.TGRA input capture/compare match
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- description: MTU0.TGRB input capture/compare match
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- description: MTU0.TGRC input capture/compare match
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- description: MTU0.TGRD input capture/compare match
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- description: MTU0.TCNT overflow
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- description: MTU0.TGRE compare match
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- description: MTU0.TGRF compare match
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- description: MTU1.TGRA input capture/compare match
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- description: MTU1.TGRB input capture/compare match
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- description: MTU1.TCNT overflow
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- description: MTU1.TCNT underflow
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- description: MTU2.TGRA input capture/compare match
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- description: MTU2.TGRB input capture/compare match
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- description: MTU2.TCNT overflow
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- description: MTU2.TCNT underflow
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- description: MTU3.TGRA input capture/compare match
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- description: MTU3.TGRB input capture/compare match
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- description: MTU3.TGRC input capture/compare match
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- description: MTU3.TGRD input capture/compare match
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- description: MTU3.TCNT overflow
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- description: MTU4.TGRA input capture/compare match
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- description: MTU4.TGRB input capture/compare match
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- description: MTU4.TGRC input capture/compare match
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- description: MTU4.TGRD input capture/compare match
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- description: MTU4.TCNT overflow/underflow
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- description: MTU5.TGRU input capture/compare match
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- description: MTU5.TGRV input capture/compare match
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- description: MTU5.TGRW input capture/compare match
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- description: MTU6.TGRA input capture/compare match
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- description: MTU6.TGRB input capture/compare match
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- description: MTU6.TGRC input capture/compare match
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- description: MTU6.TGRD input capture/compare match
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- description: MTU6.TCNT overflow
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- description: MTU7.TGRA input capture/compare match
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- description: MTU7.TGRB input capture/compare match
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- description: MTU7.TGRC input capture/compare match
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- description: MTU7.TGRD input capture/compare match
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- description: MTU7.TCNT overflow/underflow
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- description: MTU8.TGRA input capture/compare match
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- description: MTU8.TGRB input capture/compare match
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- description: MTU8.TGRC input capture/compare match
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- description: MTU8.TGRD input capture/compare match
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- description: MTU8.TCNT overflow
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- description: MTU8.TCNT underflow
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interrupt-names:
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items:
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- const: tgia0
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- const: tgib0
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- const: tgic0
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- const: tgid0
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- const: tgiv0
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- const: tgie0
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- const: tgif0
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- const: tgia1
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- const: tgib1
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- const: tgiv1
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- const: tgiu1
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- const: tgia2
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- const: tgib2
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- const: tgiv2
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- const: tgiu2
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- const: tgia3
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- const: tgib3
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- const: tgic3
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- const: tgid3
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- const: tgiv3
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- const: tgia4
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- const: tgib4
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- const: tgic4
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- const: tgid4
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- const: tgiv4
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- const: tgiu5
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- const: tgiv5
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- const: tgiw5
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- const: tgia6
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- const: tgib6
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- const: tgic6
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- const: tgid6
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- const: tgiv6
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- const: tgia7
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- const: tgib7
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- const: tgic7
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- const: tgid7
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- const: tgiv7
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- const: tgia8
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- const: tgib8
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- const: tgic8
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- const: tgid8
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- const: tgiv8
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- const: tgiu8
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clocks:
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maxItems: 1
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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"#pwm-cells":
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const: 2
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-names
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- clocks
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- power-domains
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- resets
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/r9a07g044-cpg.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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mtu3: timer@10001200 {
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compatible = "renesas,r9a07g044-mtu3", "renesas,rz-mtu3";
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reg = <0x10001200 0xb00>;
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interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 181 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 185 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 186 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 187 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 189 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 190 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 191 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 192 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 193 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 196 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 197 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 198 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 204 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 205 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 206 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 207 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", "tgiv0", "tgie0",
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"tgif0",
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"tgia1", "tgib1", "tgiv1", "tgiu1",
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"tgia2", "tgib2", "tgiv2", "tgiu2",
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"tgia3", "tgib3", "tgic3", "tgid3", "tgiv3",
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"tgia4", "tgib4", "tgic4", "tgid4", "tgiv4",
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"tgiu5", "tgiv5", "tgiw5",
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"tgia6", "tgib6", "tgic6", "tgid6", "tgiv6",
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"tgia7", "tgib7", "tgic7", "tgid7", "tgiv7",
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"tgia8", "tgib8", "tgic8", "tgid8", "tgiv8", "tgiu8";
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clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
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power-domains = <&cpg>;
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resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
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#pwm-cells = <2>;
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};
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